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    • 3. 发明授权
    • Method and apparatus for placing and detecting prewire blockages of
library cells
    • 用于放置和检测文库细胞的prewire阻塞的方法和装置
    • US5793641A
    • 1998-08-11
    • US576187
    • 1995-12-21
    • John Youssef Sayah
    • John Youssef Sayah
    • G06F17/50G06F15/00
    • G06F17/5068
    • A method and apparatus for detecting valid placement of library cells on chip images or hierarchy design images may be accomplished by determining a periodic pattern of the chip image, or hierarchical image. Once the repetitive pattern is recognized, this pattern is represented by a binary vector. Similarly, a binary vector is created for a particular cell library that is to be placed on the chip image or hierarchical design image. When the placement algorithm places the library cell on the chip or hierarchical image, the binary vector of the library cell is folded over a folded binary vector of the chip image or hierarchical design image to produce a component delta set. In essence, the component delta set indicates spacing violations between the library cell and the chip or hierarchical design image. When such a spacing violation is recognized, the placement algorithm can immediately reposition the library cell.
    • 可以通过确定芯片图像或分层图像的周期性图案来实现用于检测芯片图像或层次结构设计图像上的库单元的有效放置的方法和装置。 一旦重复模式被识别,该模式由二进制向量表示。 类似地,为要放置在芯片图像或分层设计图像上的特定单元库创建二进制向量。 当放置算法将库单元放置在芯片或分层图像上时,库单元的二进制向量在芯片图像或分层设计图像的折叠二进制向量上折叠以产生分量增量集。 本质上,组件增量集指示库单元与芯片或分层设计图像之间的间隔冲突。 当识别到这样的间隔冲突时,放置算法可以立即重新定位库单元。