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    • 5. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    • 半导体存储器件及其制造方法
    • US20110175162A1
    • 2011-07-21
    • US13009182
    • 2011-01-19
    • Joong Sik KIM
    • Joong Sik KIM
    • H01L29/78H01L21/475
    • H01L29/4236H01L27/10802H01L29/42368H01L29/7841
    • A method for fabricating a semiconductor memory device includes: forming a trench in a substrate; forming a gate insulation layer along the trench, wherein the gate insulation layer is thicker at an upper region of the trench than at a lower region thereof; forming a gate pattern on the gate insulation layer to fill the trench; forming a first active region over a first region of the gate pattern to overlap the gate pattern at the thicker region of the gate insulation layer; and forming a second active region formed over a second region of the gate pattern and spaced apart from the first active region by a floating body formed therebetween, wherein the second region is vertically lower than the first region.
    • 一种制造半导体存储器件的方法包括:在衬底中形成沟槽; 沿着所述沟槽形成栅极绝缘层,其中所述栅极绝缘层在所述沟槽的上部区域比在其较低区域处更厚; 在所述栅极绝缘层上形成栅极图案以填充所述沟槽; 在所述栅极图案的第一区域上形成第一有源区,以在所述栅极绝缘层的较厚区域处与所述栅极图案重叠; 以及形成在所述栅极图案的第二区域上形成的第二有源区,并且通过在其间形成的浮体与所述第一有源区间隔开,其中所述第二区域垂直地低于所述第一区域。
    • 6. 发明授权
    • Method for manufacturing a semiconductor device
    • 半导体器件的制造方法
    • US07727826B2
    • 2010-06-01
    • US12327362
    • 2008-12-03
    • Joong Sik KimSung Woong Chung
    • Joong Sik KimSung Woong Chung
    • H01L21/00H01L21/84
    • H01L29/7841H01L27/108H01L27/10802
    • Disclosed herein is a method for manufacturing a semiconductor device that includes forming a gate pattern on a substrate having a stacked structure including a lower silicon layer, an insulating layer, and an upper silicon layer. The method further includes forming spacers on sidewalls of the gate pattern. Still further, the method includes etching the upper silicon layer using the gate pattern as a mask to form a floating body and expose a portion of the insulating layer. The method further includes depositing a conductive layer over the gate pattern and exposed insulating layer, and performing a thermal process on the conductive layer to form a source/drain region in the floating body.
    • 本文公开了一种半导体器件的制造方法,其包括在具有下硅层,绝缘层和上硅层的层叠结构的基板上形成栅极图案。 该方法还包括在栅极图案的侧壁上形成间隔物。 此外,该方法包括使用栅极图案作为掩模蚀刻上硅层,以形成浮体并暴露绝缘层的一部分。 该方法还包括在栅极图案和暴露的绝缘层上沉积导电层,以及在导电层上执行热处理以在浮体中形成源极/漏极区域。