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1. 发明申请

US20050186715A1 Method of an array of structures sensitive to ESD and structure made therefrom 有权
标题翻译：对ESD敏感的结构阵列的方法和由其制成的结构
公开(公告)号：US20050186715A1
公开(公告)日：2005-08-25
申请号：US11040747
申请日：2005-01-24
申请人： Jr-Hong Chen , Gwo-Long Lin , Chih-Fang Chen
发明人： Jr-Hong Chen , Gwo-Long Lin , Chih-Fang Chen
IPC分类号： G02F1/1368 , G02F1/1362 , G09F9/30 , H01L21/00 , H01L21/28 , H01L21/3205 , H01L21/77 , H01L21/82 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/786
CPC分类号： H01L27/0248 , G02F1/136204 , H01L27/1214
摘要： A method of fabricating an array of structures sensitive to ESD is disclosed. First, an array of structures is provided on a substrate, with the structures conductively coupled by interconnections. Thereafter, the interconnections are removed before fabricating another array of structures. Therefore, the structures have equal potential. Further, an electrostatic discharge structure is provided near the periphery of the substrates.
摘要翻译：公开了一种制造对ESD敏感的结构阵列的方法。首先，在衬底上提供一组结构，其结构通过互连导电耦合。此后，在制造另一个结构阵列之前去除互连。因此，结构具有相同的潜力。此外，在基板的周边附近设置静电放电结构。

2. 发明授权

US06444505B1 Thin film transistor (TFT) structure with planarized gate electrode 失效
标题翻译：具有平坦化栅电极的薄膜晶体管（TFT）结构
公开(公告)号：US06444505B1
公开(公告)日：2002-09-03
申请号：US09678552
申请日：2000-10-04
申请人： Dou-I Chen , Jr-Hong Chen , Pi-Fu Chen , Wung-Ui Huang
发明人： Dou-I Chen , Jr-Hong Chen , Pi-Fu Chen , Wung-Ui Huang
IPC分类号： H01L2100
CPC分类号： H01L29/66765 , H01L29/78636
摘要： Within a method for forming a thin film transistor (TFT) structure, there is first provided a substrate. There is then formed over the substrate a gate electrode. There is then formed adjacent to the gate electrode but not covering a top surface of the gate electrode a backfilling dielectric layer. There is then formed over and covering the top surface of the gate electrode a gate dielectric layer. There is then formed over and covering the gate dielectric layer an active semiconductor layer. Finally, there is then formed over and in electrical communication with the active semiconductor layer a pair of source/drain electrodes, where the pair of source/drain electrodes having a separation distance which defines a channel region of the active semiconductor layer. The method for forming the thin film transistor (TFT) structure contemplates a thin film transistor (TFT) structure fabricated in accord with the method for forming the thin film transistor (TFT) structure. The method provides the thin film transistor (TFT) structure with enhanced functionality and reliability.
摘要翻译：在用于形成薄膜晶体管（TFT）结构的方法中，首先提供基板。然后在衬底上形成栅电极。然后形成在栅电极附近，但不覆盖栅电极的顶表面的回填电介质层。然后在栅电极的顶表面上形成栅极电介质层。然后形成并覆盖栅极电介质层有源半导体层。最后，然后在有源半导体层上形成一对源/漏电极，其中一对源极/漏极具有限定有源半导体层的沟道区的间隔距离。用于形成薄膜晶体管（TFT）结构的方法考虑了根据用于形成薄膜晶体管（TFT）结构的方法制造的薄膜晶体管（TFT）结构。该方法提供了具有增强的功能和可靠性的薄膜晶体管（TFT）结构。

3. 发明授权

US06362028B1 Method for fabricating TFT array and devices formed 有权
标题翻译：制造TFT阵列和器件的方法
公开(公告)号：US06362028B1
公开(公告)日：2002-03-26
申请号：US09377584
申请日：1999-08-19
申请人： Jr-Hong Chen , Tinghui Huang
发明人： Jr-Hong Chen , Tinghui Huang
IPC分类号： H01L2100
CPC分类号： G02F1/136213 , G02F1/136227
摘要： A method for fabricating a BCE type TFT array by using reduced number of masks and devices formed are disclosed. In the method, only five masks are required for forming the BCE type TFT array which is less than that normally required in a typical TFT fabrication process, i.e., at least six masks. The five masks required in the present invention process are a first mask for gate busline patterning, a second mask for island and S/D data line patterning, a third mask for the data line, TFT channel and Cst patterning, a fourth mask for the passivation layer patterning and a fifth mask for the conductive electrode layer patterning. The present invention novel method produces a TFT that has improved contact resistance between the S/D metal and the n+ amorphous silicon layer. The improved contact resistance is achieved by an immediate deposition process of a S/D metal thin film after the deposition of the n+ amorphous silicon layer such that any exposure of the interface to chemical contaminants and native oxide is substantially reduced or eliminated. The present invention novel method further provides the benefit that the Metal 2 layer shields the TFT island structure from plasma damages and residual photoresists resulting in a TFT array structure of improved reliability.
摘要翻译：公开了一种通过使用减少数量的掩模和形成的器件来制造BCE型TFT阵列的方法。在该方法中，形成BCE型TFT阵列仅需要五个掩膜，其小于通常在TFT制造工艺中通常所需的掩模，即至少六个掩模。在本发明方法中所需的五个掩模是用于栅极总线图案化的第一掩模，用于岛和S / D数据线图案化的第二掩模，用于数据线的第三掩模，TFT沟道和Cst图案化，第四掩模钝化层图案化和用于导电电极层图案化的第五掩模。本发明新颖的方法产生了在S / D金属和n +非晶硅层之间具有改善的接触电阻的TFT。改善的接触电阻通过在沉积n +非晶硅层之后立即沉积S / D金属薄膜来实现，使得界面对化学污染物和天然氧化物的任何暴露显着降低或消除。本发明的新颖方法还提供了金属2层屏蔽TFT岛结构免受等离子体损伤和残留光致抗蚀剂的益处，导致提高可靠性的TFT阵列结构。

4. 发明授权

US07884899B2 System for displaying images and method with a peripheral region having a mosaic color filter pattern thereon that has pillars and channels and an opening along its boundary 有权
标题翻译：用于显示图像和方法的系统，具有其上具有柱和通道的马赛克滤色器图案的外围区域和沿其边界的开口
公开(公告)号：US07884899B2
公开(公告)日：2011-02-08
申请号：US11670549
申请日：2007-02-02
申请人： Yao-Pin Hsu , Chi-Wen Peng , Cheng-Hsin Chen , Jr-Hong Chen
发明人： Yao-Pin Hsu , Chi-Wen Peng , Cheng-Hsin Chen , Jr-Hong Chen
IPC分类号： G02F1/1335
CPC分类号： G02F1/133516 , G02F2001/133388 , G02F2001/133519
摘要： Systems for displaying images and methods for fabricating the same. A representative system includes a substrate having a display region and a peripheral region, and a mosaic color filter pattern formed in the peripheral region. The mosaic color filter pattern includes a plurality of separated pillars and a plurality of channels adjacent to the pillars. Specifically the volume ratio between the pillars and the channel is 1:5 to 2:1, preferably 1:3 to 1:1.
摘要翻译：用于显示图像的系统及其制造方法。代表性系统包括具有显示区域和周边区域的基板和形成在周边区域中的马赛克滤色器图案。马赛克滤色器图案包括多个分离的柱和与柱相邻的多个通道。具体地说，柱和通道之间的体积比为1:5至2:1，优选1:3至1:1。

5. 发明授权

US06323034B1 Amorphous TFT process 有权
标题翻译：非晶TFT工艺
公开(公告)号：US06323034B1
公开(公告)日：2001-11-27
申请号：US09373250
申请日：1999-08-12
申请人： Yeong-E Chen , Jr-Hong Chen , Ya-Hsiang Tai
发明人： Yeong-E Chen , Jr-Hong Chen , Ya-Hsiang Tai
IPC分类号： H01L2100
CPC分类号： H01L29/66765 , H01L29/41733
摘要： A thin film transistor design is described which is not subject to either dark or photo current leakage. The process to manufacture this device begins with the formation of a gate electrode on a transparent substrate followed by its over coating with layers of gate insulation, undoped amorphous silicon, doped amorphous silicon, and a second layer of chromium. The chromium and amorphous silicon layers are then patterned and etched to form a channel pedestal. In a key feature of the invention the vertical side walls of this pedestal are then given a protective coating of oxide or nitride, forming spacers. This is then followed by the deposition of second level metal which is etched to form source and drain electrodes with a suitable gap between them.
摘要翻译：描述了不受暗或光电流泄漏的薄膜晶体管设计。制造该器件的过程开始于在透明衬底上形成栅电极，然后在其上涂覆栅极绝缘层，未掺杂的非晶硅，掺杂的非晶硅和第二层的铬。然后将铬和非晶硅层图案化并蚀刻以形成通道基座。在本发明的关键特征中，该基座的垂直侧壁然后被赋予氧化物或氮化物的保护涂层，形成间隔物。然后，沉积第二级金属，其被蚀刻以形成在它们之间具有合适间隙的源极和漏极。

6. 发明授权

US5656197A Ferroelectric liquid crystal 失效
标题翻译：铁电液晶
公开(公告)号：US5656197A
公开(公告)日：1997-08-12
申请号：US384027
申请日：1995-02-06
申请人： Ging-Ho Hsiue , Jr-Hong Chen , Rong-Chi Chang
发明人： Ging-Ho Hsiue , Jr-Hong Chen , Rong-Chi Chang
IPC分类号： C08G77/38 , C09K19/40 , C09K19/52 , C08G77/04 , C09K19/20
CPC分类号： C08G77/38 , C09K19/408
摘要： A polymer of the following formula: ##STR1## wherein m is an integer from 1 to 100; n is an integer from 0 to 3; each of X and Y, independently, is biphenyl, 1,4-phenylene, or halogen-substituted 1,4-phenylene; and Z is R, --O--(C.dbd.O)--R, or --(C.dbd.O)--O--R, wherein R is selected from (2R)-2-(C.sub.4-8 alkyl), (1S,2S)-1-halo-2-methyl-1-(C.sub.3-5 alkyl), (2S)-2-methyl-1-(C.sub.4-7 alkyl), (2S)-1-halo-2-methyl-3-propyl, and (2S)-3-halo-2-methyl-1-(C.sub.4-7 alkyl); anda monomer of the following formula:H.sub.2 C.dbd.CH.sub.2 CH.sub.2 --(OCH.sub.2 CH.sub.2).sub.n --O--X--(C.dbd.O)--O--Y--Zwherein n is an integer from 0 to 3; each of X and Y independently is biphenyl, 1,4-phenylene, or halogen-substituted 1,4-phenylene; and Z is R, --O--(C.dbd.O)--R, or --(C.dbd.O)--O--R, wherein R is selected from (2R)-2-(C.sub.4-8 alkyl), (1S,2S)-1-halo-2-methyl-1-(C.sub.3-5 alkyl), (2S)-2-methyl-1-(C.sub.5-7 alkyl), (2S)-1-halo-2-methyl-3-propyl, and (2S)-3-halo-2-methyl-1-(C.sub.4-7 alkyl).
摘要翻译：下式的聚合物：其中m是1至100的整数; n为0〜3的整数。 X和Y各自独立地是联苯基，1,4-亚苯基或卤素取代的1,4-亚苯基; 并且Z为R，-O-（C = O）-R或 - （C = O）-OR，其中R选自（2R）-2-（C 4-8烷基），（1S，2S） - 1-卤代-2-甲基-1-（C3-5烷基），（2S）-2-甲基-1-（C4-7烷基），（2S）-1-卤代-2-甲基-3-丙基，和（2S）-3-卤代-2-甲基-1-（C 4-7烷基）; 和下式的单体：H 2 C = CH 2 CH 2 - （OCH 2 CH 2）n-O-X-（C = O）-O-Y-Z其中n为0-3的整数; X和Y各自独立地是联苯基，1,4-亚苯基或卤素取代的1,4-亚苯基; 并且Z为R，-O-（C = O）-R或 - （C = O）-OR，其中R选自（2R）-2-（C 4-8烷基），（1S，2S） - 1-（2-甲基-1-（C 5-8烷基），（2S）-2-甲基-1-（C 5-7烷基），（2S）-1-卤代-2-甲基-3-丙基，和（2S）-3-卤代-2-甲基-1-（C 4-7烷基）。

7. 发明授权

US07332379B2 Method of an array of structures sensitive to ESD and structure made therefrom 有权
标题翻译：对ESD敏感的结构阵列的方法和由其制成的结构
公开(公告)号：US07332379B2
公开(公告)日：2008-02-19
申请号：US11040747
申请日：2005-01-21
申请人： Jr-Hong Chen , Gwo-Long Lin , Chih-Fang Chen
发明人： Jr-Hong Chen , Gwo-Long Lin , Chih-Fang Chen
IPC分类号： H01L21/82
CPC分类号： H01L27/0248 , G02F1/136204 , H01L27/1214
摘要： A method of fabricating an array of structures sensitive to ESD is disclosed. First, an array of structures is provided on a substrate, with the structures conductively coupled by interconnections. Thereafter, the interconnections are removed before fabricating another array of structures. Therefore, the structures have equal potential. Further, an electrostatic discharge structure is provided near the periphery of the substrates.
摘要翻译：公开了一种制造对ESD敏感的结构阵列的方法。首先，在衬底上提供一组结构，其结构通过互连导电耦合。此后，在制造另一个结构阵列之前去除互连。因此，结构具有相同的潜力。此外，在基板的周边附近设置静电放电结构。

8. 发明申请

US20060118787A1 Electronic device with electrostatic discharge protection 审中-公开
标题翻译：具有静电放电保护的电子设备
公开(公告)号：US20060118787A1
公开(公告)日：2006-06-08
申请号：US11003215
申请日：2004-12-02
申请人： Yi-Hsing Lee , Chu-Jung Shih , Jr-Hong Chen
发明人： Yi-Hsing Lee , Chu-Jung Shih , Jr-Hong Chen
IPC分类号： H01L29/10
CPC分类号： H01L27/124 , H01L27/0251
摘要： Electronic devices with electrostatic discharge protection are provided. The electronic devices can comprise an array substrate with electrostatic discharge (ESD) protection, having a substrate, a plurality of conductive lines overlying the substrate along a first direction and at least one conductive segment overlying the substrate between every two conductive lines, wherein each conductive segment is electrically isolated from the conductive lines.
摘要翻译：提供具有静电放电保护的电子设备。电子器件可以包括具有静电放电（ESD）保护的阵列衬底，具有衬底，沿着第一方向覆盖衬底的多条导线和在每两条导线之间覆盖衬底的至少一个导电段，其中每个导电段与导电线电隔离。

9. 发明授权

US06552361B1 Thin film transistor device 有权
标题翻译：薄膜晶体管器件
公开(公告)号：US06552361B1
公开(公告)日：2003-04-22
申请号：US09680935
申请日：2000-10-10
申请人： I-Min Lu , Jr-Hong Chen
发明人： I-Min Lu , Jr-Hong Chen
IPC分类号： H01L2904
CPC分类号： H01L29/78636
摘要： A thin film transistor (TFT) and method of fabricating the same. A planarization layer of polymer is formed on the interlayer to reduce short-circuit. The planarization layer further reduces the capacitance of the crossover capacitor and the delay time of the LCD panel using the TFT is therefor minimized. A gate thereof can be design under the data line to increase aperture ratio.
摘要翻译：薄膜晶体管（TFT）及其制造方法。在中间层上形成聚合物的平坦化层以减少短路。平坦化层进一步降低了交叉电容器的电容，并且使用TFT的LCD面板的延迟时间被最小化。其栅极可以在数据线下设计以增加开口率。

10. 发明授权

US06466281B1 Integrated black matrix/color filter structure for TFT-LCD 有权
标题翻译：用于TFT-LCD的集成黑矩阵/滤色器结构
公开(公告)号：US06466281B1
公开(公告)日：2002-10-15
申请号：US09378965
申请日：1999-08-23
申请人： Tinghui Huang , Jr-Hong Chen , Biing Der Liu
发明人： Tinghui Huang , Jr-Hong Chen , Biing Der Liu
IPC分类号： G02F1136
CPC分类号： G02F1/136209 , G02F1/136213 , G02F1/136227 , G02F2001/136222
摘要： An active cell for a thin-film transistor liquid crystal display, with integrated black matrix/color filter, includes a switching device, a data line, a scanning line, a planarization layer, a light shielding layer, a dielectric layer, a first electrode layer, a liquid crystal layer, a second electrode layer, and a counter plate. The switching device is formed on the substrate, wherein the data line supplies data signals to the switching device and the scanning line supplies controlling signals to the switching device. The planarization layer is formed on the switching device and has a contact opening which is extended down to a driven end of the switching device. The light shielding layer is on a portion of the planarization layer and the dielectric layer is on the light shielding layer and a top planar region of the planarization layer. The first electrode layer is formed on the dielectric layer and the planarization layer, and the first electrode layer also communicates to the driven end of the switching device through the contact opening. The liquid crystal layer is on the substrate, the second electrode layer is on the liquid crystal layer, and the counter plate on the second electrode layer.
摘要翻译：具有集成黑矩阵/滤色器的薄膜晶体管液晶显示器的有源电池包括开关器件，数据线，扫描线，平坦化层，遮光层，电介质层，第一电极层，液晶层，第二电极层和对置板。切换装置形成在基板上，其中数据线向开关装置提供数据信号，扫描线向开关装置提供控制信号。平面化层形成在开关装置上，并且具有向下延伸到开关装置的驱动端的接触开口。遮光层位于平坦化层的一部分上，并且介电层位于遮光层和平坦化层的顶部平面区域上。第一电极层形成在电介质层和平坦化层上，第一电极层也通过接触开口与开关装置的驱动端连通。液晶层位于基板上，第二电极层位于液晶层上，第二电极层位于第二电极层上。

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