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    • 4. 发明申请
    • Semiconductor programmable device
    • 半导体可编程器件
    • US20050104129A1
    • 2005-05-19
    • US10817777
    • 2004-04-02
    • Jui-Lung ChenYang-Chen HsuChien-Jiun Wang
    • Jui-Lung ChenYang-Chen HsuChien-Jiun Wang
    • H01L27/06H01L29/76H01L29/94H01L31/062
    • H01L27/0629
    • A semiconductor programmable device is provided. The semiconductor programmable device comprises a P-type substrate, an N-well, an NMOS capacitor and a PMOS transistor. The N-well is formed in the P-type substrate. The NMOS capacitor is configured on the P-type substrate. The PMOS transistor is configured on the N-well. A source/drain of the PMOS transistor is electrically connected to a gate of the NMOS capacitor. A control voltage is applied to a gate of the PMOS transistor. A programming voltage is applied to the source/drain of the PMOS transistor. The programming voltage is large enough to cause a breakdown of a gate oxide layer of the NMOS capacitor. The gate oxide layer of the NMOS capacitor has a thickness identical to the gate oxide layer of the PMOS transistor.
    • 提供半导体可编程器件。 半导体可编程器件包括P型衬底,N阱,NMOS电容器和PMOS晶体管。 在P型衬底中形成N阱。 NMOS电容器配置在P型基板上。 PMOS晶体管配置在N阱上。 PMOS晶体管的源极/漏极电连接到NMOS电容器的栅极。 控制电压施加到PMOS晶体管的栅极。 对PMOS晶体管的源极/漏极施加编程电压。 编程电压足够大,导致NMOS电容器的栅极氧化层的击穿。 NMOS电容器的栅极氧化层具有与PMOS晶体管的栅氧化层相同的厚度。
    • 7. 发明申请
    • MEMORY AND STORAGE DEVICE UTILIZING THE SAME
    • 使用该存储器和存储器件的存储器和存储器件
    • US20100315852A1
    • 2010-12-16
    • US12484088
    • 2009-06-12
    • Jui-Lung Chen
    • Jui-Lung Chen
    • G11C5/02G11C7/00
    • G11C8/08G11C17/12G11C2207/005
    • A storage device including a memory and a reading circuit is disclosed. The memory includes a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the third bit lines are sequentially disposed in parallel and vertical with the word lines. Each cell corresponds to one word line and one bit line. The word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The read circuit is coupled to the memory for reading the data stored in the memory.
    • 公开了一种包括存储器和读取电路的存储装置。 存储器包括多个字线,第一位线,第二位线,第三位线和多个单元。 字线顺序地并列设置。 第一,第二和第三位线与字线平行且垂直地顺序地布置。 每个单元对应一个字线和一个位线。 对应于与第一位线对应的单元的字线与对应于第二位线的单元的字线不同。 读取电路耦合到存储器,用于读取存储在存储器中的数据。
    • 8. 发明申请
    • ASYMMETRIC STATIC RANDOM ACCESS MEMORY
    • 不对称静态随机存取存储器
    • US20100177556A1
    • 2010-07-15
    • US12351772
    • 2009-01-09
    • Jui-Lung ChenWei-Shung ChenYi-Hsun ChungChia-Chiuan Chang
    • Jui-Lung ChenWei-Shung ChenYi-Hsun ChungChia-Chiuan Chang
    • G11C11/00G11C5/14
    • G11C11/412
    • An asymmetric static random access memory (SRAM) device that includes at least one SRAM cell is provided. The SRAM cell includes the first inverter and the second inverter. The first inverter is coupled between a first power and a ground power, and includes a first output terminal coupled to a first node and a first input terminal coupled to a second node. The second inverter is coupled between the first power and the ground power, and includes a second input terminal coupled to the first node and a second output terminal coupled to the second node. When the first inverter and the second inverter receive current from the first power, the SRAM cell is programmed to a predetermined value in advance according to different conductance levels of the first inverter and the second inverter.
    • 提供了包括至少一个SRAM单元的非对称静态随机存取存储器(SRAM)器件。 SRAM单元包括第一反相器和第二反相器。 第一反相器耦合在第一功率和地功率之间,并且包括耦合到第一节点的第一输出端和耦合到第二节点的第一输入端。 第二反相器耦合在第一电源和地电之间,并且包括耦合到第一节点的第二输入端和耦合到第二节点的第二输出端。 当第一逆变器和第二逆变器从第一功率接收电流时,根据第一逆变器和第二逆变器的不同电导电平,预先将SRAM单元编程为预定值。