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    • 1. 发明授权
    • Semiconductor memory device and method of manufacturing same
    • 半导体存储器件及其制造方法
    • US08309958B2
    • 2012-11-13
    • US12872284
    • 2010-08-31
    • Jun HirotaYoko IwakajiMoto Yabuki
    • Jun HirotaYoko IwakajiMoto Yabuki
    • H01L29/06H01L29/12H01L45/00
    • H01L27/1021H01L27/101
    • According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.
    • 根据一个实施例,半导体存储器件包括字线互连层,位线互连层和柱。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿与第一方向交叉的第二方向延伸的多个位线。 支柱布置在每个字线和每个位线之间。 支柱包括硅二极管和可变电阻膜,并且硅二极管包括p型部分和n型部分。 字线互连层和位线互连层交替堆叠,并且在p型部分和n型部分变得更接近的方向上对硅二极管施加压缩力。
    • 3. 发明授权
    • Nonvolatile memory device
    • 非易失性存储器件
    • US08664631B2
    • 2014-03-04
    • US13236713
    • 2011-09-20
    • Jun HirotaYoko IwakajiMoto Yabuki
    • Jun HirotaYoko IwakajiMoto Yabuki
    • H01L45/00
    • H01L45/04H01L27/2409H01L27/2481H01L45/1233H01L45/145H01L45/1675
    • According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.
    • 根据一个实施例,非易失性存储器件包括字线互连层,位线互连层,柱和电荷承载部件。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿与第一方向相交的第二方向延伸的多个位线。 支柱设置在每个字线和每个位线之间。 电荷承载部件包含负的固定电荷,并且设置在支柱的侧面上。 支柱包括二极管膜,该二极管膜设置有层叠在二极管膜上的p型层和n型层以及可变电阻膜。 电荷承载部件配置在p型层的侧面,不配置在n型层的侧面。
    • 10. 发明申请
    • NONVOLATILE MEMORY DEVICE
    • 非易失性存储器件
    • US20120235107A1
    • 2012-09-20
    • US13236713
    • 2011-09-20
    • Jun HirotaYoko IwakajiMoto Yabuki
    • Jun HirotaYoko IwakajiMoto Yabuki
    • H01L45/00
    • H01L45/04H01L27/2409H01L27/2481H01L45/1233H01L45/145H01L45/1675
    • According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.
    • 根据一个实施例,非易失性存储器件包括字线互连层,位线互连层,柱和电荷承载部件。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿与第一方向相交的第二方向延伸的多个位线。 支柱设置在每个字线和每个位线之间。 电荷承载部件包含负的固定电荷,并且设置在支柱的侧面上。 支柱包括二极管膜,该二极管膜设置有层叠在二极管膜上的p型层和n型层以及可变电阻膜。 电荷承载部件配置在p型层的侧面,不配置在n型层的侧面。