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1. 发明授权

US10074778B2 Light emitting diode package and method for manufacturing the same 有权
公开(公告)号：US10074778B2
公开(公告)日：2018-09-11
申请号：US13425156
申请日：2012-03-20
申请人： Chi Hyun In , Jun Yong Park , Kyu Ho Lee , Dae Woong Suh , Jong Hyeon Chae , Chang Hoon Kim , Sung Hyun Lee
发明人： Chi Hyun In , Jun Yong Park , Kyu Ho Lee , Dae Woong Suh , Jong Hyeon Chae , Chang Hoon Kim , Sung Hyun Lee
IPC分类号： H01L33/50 , H01L33/62 , H01L33/48 , H01L33/20 , H01L33/44
CPC分类号： H01L33/486 , H01L33/20 , H01L33/44 , H01L33/505 , H01L33/62 , H01L2224/16 , H01L2933/0033
摘要： Disclosed herein are a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes: a substrate, a light-emitting layer disposed on a surface of the substrate and including a first type semiconductor layer, an active layer, and a second type semiconductor layer, a first bump disposed on the first type semiconductor layer and a second bump disposed the second type semiconductor layer, a protective layer covering at least the light-emitting layer, and a first bump pad and a second bump pad disposed on the protective layer and connected to the first bump and the second bump, respectively.

2. 发明申请

US20120014187A1 Non-volatile memory device and method of operation therefor 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20120014187A1
公开(公告)日：2012-01-19
申请号：US13200361
申请日：2011-09-23
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.
摘要翻译：在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。在阱外部的衬底中形成缓冲器，并连接到位线。至少一个去耦合晶体管被配置为从位线去耦合缓冲器，并且在阱中形成去耦合晶体管。

3. 发明授权

US06697692B2 Control system of factory automation facility for seatbelt retractor assembly and method thereof 失效
公开(公告)号：US06697692B2
公开(公告)日：2004-02-24
申请号：US10079808
申请日：2002-02-22
申请人： Taek Kwang Kim , Jun Yong Park , Byung Gul Choi , Dong Sub Lee
发明人： Taek Kwang Kim , Jun Yong Park , Byung Gul Choi , Dong Sub Lee
IPC分类号： G06F1900
CPC分类号： G05B19/4145 , B60R22/34 , G05B2219/34288
摘要： a control system of a factory automation facility for a seatbelt retractor assembly comprising a factory automation facility and a control portion for controlling the operating of all parts in the factory automation facility, integrally, to enable the mass-production of a seatbelt retractor assembly, in which the factory automation facility comprises a webbing throwing-in portion for throwing-in a webbing of a strip type thereinto by a first webbing supplying portion; first and second webbing position determining devices for guiding the webbing to pass through the hole of a retractor spool, a webbing withdrawing portion including a second webbing supplying portion and a case to withdraw the webbing and store it for a while, first and second part supplying portions for assembling a tongue, a guide ring and a ring mount on the withdrawn webbing, a stopper fixing portion including a third webbing supplying portion for carrying the webbing to a webbing folding portion, upper and lower stopper suppliers for supplying upper and lower to be mounted on both surfaces of the webbing, respectively, and a stopper pressing portions for coupling the upper and lower stopper parts with each other on the other side of the webbing; and a webbing folding portion for folding the front end of the webbing by the reference of its center in a longitudinal direction and coupling the folded end to an end mount, and the control portion perform routines of turning on the power of a system to force the portions of the factory automation facility to be ready for their operating; throwing-in a webbing into a retractor; withdrawing the webbing from the retractor; carrying the webbing to a proper position so as to press upper and lower stoppers on the webbing; pressing the upper and lower stoppers to be arranged on the other side of the webbing; and pressing the upper and lower stoppers to be coupled to each other and folding the front end of the webbing to be coupled with an end mount.

4. 发明授权

US08120253B2 Plasma display panel 失效
标题翻译：等离子显示面板
公开(公告)号：US08120253B2
公开(公告)日：2012-02-21
申请号：US12274964
申请日：2008-11-20
申请人： Mun-Ho Nam , Jun-Yong Park
发明人： Mun-Ho Nam , Jun-Yong Park
IPC分类号： H01J17/49
CPC分类号： H01J11/40 , H01J11/12 , H01J11/36 , H01J2211/323 , H01J2211/365
摘要： A plasma display panel (PDP) with improved address voltage margin and reduced noise brightness such as discharge light or background light during an address discharge. The PDP includes a plurality of barrier ribs between a front substrate and a rear substrate to define a plurality of main discharge spaces and a plurality of auxiliary discharge spaces along a stepped surface of the barrier ribs. The auxiliary discharge spaces provide a shorter discharge path than the main discharge spaces. Address electrodes are provided on the rear substrate for generating address discharges together with the scan electrodes on the front substrate at locations adjacent to the auxiliary discharge spaces. Phosphor layers are respectively formed in the main discharge spaces, and a discharge gas is injected in the main discharge spaces and the auxiliary discharge spaces.
摘要翻译：一种等离子体显示面板（PDP），其在地址放电期间具有改善的寻址电压余量和降低的噪声亮度，例如放电光或背景光。 PDP包括在前基板和后基板之间的多个隔壁，以在隔壁的台阶表面上限定多个主放电空间和多个辅助放电空间。辅助放电空间提供比主放电空间更短的放电路径。地址电极设置在后基板上，用于与邻近辅助放电空间的位置处的前基板上的扫描电极一起产生寻址放电。在主放电空间中分别形成荧光体层，并且在主放电空间和辅助放电空间中注入放电气体。

5. 发明申请

US20090128035A1 PLASMA DISPLAY PANEL 失效
标题翻译：等离子显示面板
公开(公告)号：US20090128035A1
公开(公告)日：2009-05-21
申请号：US12274964
申请日：2008-11-20
申请人： Mun-Ho Nam , Jun-Yong Park
发明人： Mun-Ho Nam , Jun-Yong Park
IPC分类号： H01J17/49
CPC分类号： H01J11/40 , H01J11/12 , H01J11/36 , H01J2211/323 , H01J2211/365
摘要： A plasma display panel (PDP) with improved address voltage margin and reduced noise brightness such as discharge light or background light during an address discharge. The PDP includes a plurality of barrier ribs between a front substrate and a rear substrate to define a plurality of main discharge spaces and a plurality of auxiliary discharge spaces along a stepped surface of the barrier ribs. The auxiliary discharge spaces provide a shorter discharge path than the main discharge spaces. Address electrodes are provided on the rear substrate for generating address discharges together with the scan electrodes on the front substrate at locations adjacent to the auxiliary discharge spaces. Phosphor layers are respectively formed in the main discharge spaces, and a discharge gas is injected in the main discharge spaces and the auxiliary discharge spaces.
摘要翻译：一种等离子体显示面板（PDP），其在地址放电期间具有改善的寻址电压余量和降低的噪声亮度，例如放电光或背景光。 PDP包括在前基板和后基板之间的多个隔壁，以在隔壁的台阶表面上限定多个主放电空间和多个辅助放电空间。辅助放电空间提供比主放电空间更短的放电路径。地址电极设置在后基板上，用于与邻近辅助放电空间的位置处的前基板上的扫描电极一起产生寻址放电。在主放电空间中分别形成荧光体层，并且在主放电空间和辅助放电空间中注入放电气体。

6. 发明授权

US07504775B2 Plasma display panel (PDP) 失效
标题翻译：等离子显示面板（PDP）
公开(公告)号：US07504775B2
公开(公告)日：2009-03-17
申请号：US11117554
申请日：2005-04-29
申请人： Su-Bin Song , Kyoung-Doo Kang , Jun-Yong Park , Won-Ju Yi
发明人： Su-Bin Song , Kyoung-Doo Kang , Jun-Yong Park , Won-Ju Yi
IPC分类号： H01J17/49
CPC分类号： H01J11/16 , H01J11/24 , H01J11/32 , H01J2211/245 , H01J2211/323
摘要： A Plasma Display Panel (PDP) has a high aperture ratio of a discharge cell, a high light transmittance, and a high luminous efficiency and a stable and efficient discharge occurs uniformly at a low driving voltage on inner sidewalls of the discharge cell and concentrates in the center of the discharge cell. The PDP includes: a front substrate and a rear substrate facing each other and separated from each other; barrier ribs of a dielectric material arranged between the front substrate and the rear substrate to define discharge cells together with the front substrate and the rear substrate; discharge electrodes arranged within the barrier ribs, the discharge electrodes being separated from each other and surrounding the discharge cells and having at least one corner portion for surrounding the discharge cells; fluorescent layers arranged in the discharge cells; a discharge gas contained within the discharge cells; and an attenuator adapted to reduce a strength of an electric field generated between at least one pair of corner portions of the discharge electrodes, the corner portions facing each other, to be less than a strength of an electric field generated between portions of the discharge electrodes facing each other, other than the corner portions, in the discharge cells.
摘要翻译：等离子体显示面板（PDP）具有放电单元的高开口率，高透光率和高发光效率，并且在放电单元的内侧壁上的低驱动电压下均匀地发生稳定且高效的放电，并且集中在放电单元的中心。 PDP包括：彼此面对并分离的前基板和后基板; 布置在前基板和后基板之间的介电材料的阻挡肋以与前基板和后基板一起限定放电单元; 布置在阻挡肋内的放电电极，放电电极彼此分离并且围绕放电单元并且具有用于包围放电单元的至少一个角部; 布置在放电单元中的荧光层; 包含在放电单元内的放电气体; 以及衰减器，其适于减小在所述放电电极的至少一对角部之间产生的电场的强度，所述角部彼此面对，以小于所述放电电极的部分之间产生的电场的强度在放电单元中彼此面对，而不是角部。

7. 发明授权

US08339851B2 Non-volatile memory device and method of operation therefor 失效
公开(公告)号：US08339851B2
公开(公告)日：2012-12-25
申请号：US13200361
申请日：2011-09-23
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

8. 发明授权

US08149621B2 Flash memory device and method of testing the flash memory device 有权
标题翻译：闪存设备和测试闪存设备的方法
公开(公告)号：US08149621B2
公开(公告)日：2012-04-03
申请号：US12585725
申请日：2009-09-23
申请人： Bo-geun Kim , Dae-yong Kim , Jun-yong Park
发明人： Bo-geun Kim , Dae-yong Kim , Jun-yong Park
IPC分类号： G11C11/34
CPC分类号： G11C29/12 , G11C16/04 , G11C2029/1208
摘要： A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.
摘要翻译：提供一种闪存设备和测试闪存设备的方法。闪存器件可以包括包括多个位线的存储单元阵列，被配置为输出估计数据的控制单元和包括多个页缓冲器的输入/输出缓冲单元。多个页缓冲器中的每一个对应于存储单元阵列中的多个位线之一，并且被配置为读取在存储单元阵列的至少第一页中编程的测试数据，将读出的测试数据与估计数据，以确定对应的位线是否处于通过或故障状态，并输出测试结果信号。如果第一页中的相应位线处于故障状态，则读取存储单元阵列的第二页的测试数据时，维持测试结果信号的电压。

9. 发明申请

US20120020167A1 FLASH MEMORY DEVICE AND A METHOD OF PROGRAMMING THE SAME 有权
标题翻译：闪存存储器件及其编程方法
公开(公告)号：US20120020167A1
公开(公告)日：2012-01-26
申请号：US13170713
申请日：2011-06-28
申请人： Jong-hoon Lee , Jun-yong Park
发明人： Jong-hoon Lee , Jun-yong Park
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device.
摘要翻译：闪存器件包括包括多个存储器单元的存储单元阵列; 产生并输出位线电压控制信号的位线电压控制信号发生器; 以及通过多个位线连接到存储单元阵列的页面缓冲单元，并且响应于从位线电压控制信号发生器输出的位线电压控制信号来控制多个位线的电压电平，其中多个位线位线包括与第一位线相邻的第一位线和第二位线，其中在位线预充电操作期间，第一位线处于程序禁止状态，第二位线处于编程中状态，所述页缓冲器单元响应于所述位线电压控制信号而增加所述第一位线的电压电平，其中所述第一位线的电压电平的增加导致所述第二位线的电压电平增加，以及其中所述位线电压控制信号的电压电平不受所述闪存器件的电源电压的变化的影响。

10. 发明授权

US08081509B2 Non-volatile memory device and method of operation therefor 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US08081509B2
公开(公告)日：2011-12-20
申请号：US12662571
申请日：2010-04-23
申请人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
发明人： Dae-Yong Kim , Sang-Won Hwang , Jun-Yong Park
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.
摘要翻译：在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。在阱外部的衬底中形成缓冲器，并连接到位线。至少一个去耦合晶体管被配置为从位线去耦合缓冲器; 并且在阱中形成去耦合晶体管。

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