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1. 发明授权

US08799730B2 Semiconductor devices and semiconductor packages 有权
标题翻译：半导体器件和半导体封装
公开(公告)号：US08799730B2
公开(公告)日：2014-08-05
申请号：US13453447
申请日：2012-04-23
申请人： Chi-sung Oh , Jung-sik Kim , Ho-cheol Lee , Jung-bae Lee
发明人： Chi-sung Oh , Jung-sik Kim , Ho-cheol Lee , Jung-bae Lee
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/40 , G01R31/3187
CPC分类号： G01R31/318555 , G01R31/318538 , G01R31/318597 , G01R31/3187 , H01L22/32 , H01L23/481 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13541 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/81193 , H01L2924/12042 , H01L2924/15192 , H01L2924/014 , H01L2924/00014 , H01L2924/00 , H01L2924/206
摘要： Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.
摘要翻译：半导体器件被配置为测试包括一个或多个微凸块的微凸块和边界扫描测试块的连接性，用于通过扫描输入到微凸块的数据并输出扫描数据来测试微凸块的连接性。半导体器件可以包括第一芯片，其包括焊球和与各个焊球电耦合的至少一个或多个开关，以及堆叠在第一芯片的顶部上并与直流存取模式的开关电耦合的第二芯片，包括微从焊球传出的输入/输出信号的凸起。

2. 发明授权

US08482951B2 Memory device from which dummy edge memory block is removed 有权
标题翻译：去除虚拟边缘存储器块的存储器件
公开(公告)号：US08482951B2
公开(公告)日：2013-07-09
申请号：US13023738
申请日：2011-02-09
申请人： Chul-woo Yi , Seong-jin Jang , Jin-seok Kwak , Tai-young Ko , Joung-yeal Kim , Sang-yun Kim , Sang-kyun Park , Jung-bae Lee
发明人： Chul-woo Yi , Seong-jin Jang , Jin-seok Kwak , Tai-young Ko , Joung-yeal Kim , Sang-yun Kim , Sang-kyun Park , Jung-bae Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/063 , G11C7/062 , G11C7/065 , G11C7/18 , G11C11/4091 , G11C11/4097 , H01L27/0207 , H01L27/105 , H01L27/10885 , H01L27/10897 , Y10T29/41
摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.
摘要翻译：一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管，电容器块电连接到边缘检测放大块。

3. 发明授权

US08395953B2 Bit-line sense amplifier, semiconductor memory device having the same, and method of testing bit-line micro-bridge defect 有权
标题翻译：位线读出放大器，具有相同的半导体存储器件以及测试位线微桥缺陷的方法
公开(公告)号：US08395953B2
公开(公告)日：2013-03-12
申请号：US12958726
申请日：2010-12-02
申请人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
发明人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C29/025 , G11C29/12005 , G11C29/1201 , G11C2029/1204
摘要： The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.
摘要翻译：位线读出放大器包括驱动电压控制电路和放大器。驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。放大器感测并放大位线和互补位线之间的电压差。

4. 发明授权

US08391095B2 Method controlling deep power down mode in multi-port semiconductor memory 有权
标题翻译：在多端口半导体存储器中控制深度掉电模式的方法
公开(公告)号：US08391095B2
公开(公告)日：2013-03-05
申请号：US12768060
申请日：2010-04-27
申请人： Ho-Cheol Lee , Jung-Bae Lee
发明人： Ho-Cheol Lee , Jung-Bae Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C5/144 , G11C5/147 , G11C8/16
摘要： Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.
摘要翻译：公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

5. 发明授权

US08362539B2 Semiconductor device and semiconductor package including the same 有权
标题翻译：半导体器件和包括其的半导体封装
公开(公告)号：US08362539B2
公开(公告)日：2013-01-29
申请号：US12458874
申请日：2009-07-27
申请人： Ki-Whan Song , Jung-Bae Lee
发明人： Ki-Whan Song , Jung-Bae Lee
IPC分类号： H01L27/108
CPC分类号： H01L23/481 , H01L24/48 , H01L25/0657 , H01L2224/48227 , H01L2224/73257 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a first substrate including at least one first well region and first impurity regions on portions of the substrate and a bias voltage plate on a surface of the substrate. A semiconductor device may be of a three dimensional stack structure, and in example embodiments, the semiconductor device may further include a through contact plug substantially perpendicularly penetrating at least one substrate and at least one bias voltage plate. Therefore, a design margin of a semiconductor device may be enhanced and a bias voltage may be provided reliably.
摘要翻译：半导体器件包括：第一衬底，包括至少一个第一阱区域和衬底的部分上的第一杂质区域以及衬底表面上的偏压板。半导体器件可以是三维堆叠结构，并且在示例性实施例中，半导体器件还可以包括基本垂直地穿透至少一个衬底和至少一个偏置电压板的贯穿接触插塞。因此，可以提高半导体器件的设计裕度，并且可以可靠地提供偏置电压。

6. 发明授权

US08205135B2 Memory system and command handling method 有权
标题翻译：内存系统和命令处理方法
公开(公告)号：US08205135B2
公开(公告)日：2012-06-19
申请号：US13228763
申请日：2011-09-09
申请人： Jung-Bae Lee
发明人： Jung-Bae Lee
IPC分类号： H03M13/00
CPC分类号： G06F11/1008
摘要： A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.
摘要翻译：公开了一种包括存储器控制器和存储器以及相关方法的存储器系统。该方法包括将与命令相关联的命令和错误检测/校正（EDC）数据从存储器控制器传送到存储器，解码该命令并并行执行与EDC数据相关的EDC操作，并且如果命令是写入命令，延迟执行由写入命令指示的写入操作，直到完成EDC操作，否则立即执行由命令指示的操作，而不考虑完成EDC操作。

7. 发明授权

US08154934B2 Semiconductor memory device and memory system having the same 有权
标题翻译：半导体存储器件和具有该半导体存储器件的存储器系统
公开(公告)号：US08154934B2
公开(公告)日：2012-04-10
申请号：US12788029
申请日：2010-05-26
申请人： Ho-Young Kim , Ho-Cheol Lee , Jung-Bae Lee
发明人： Ho-Young Kim , Ho-Cheol Lee , Jung-Bae Lee
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/222 , G11C2207/2272
摘要： A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.
摘要翻译：公开了一种半导体存储器件。半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号阵列并响应于内部时钟信号输出读取数据信号。半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号内部时钟信号。

8. 发明申请

US20110314349A1 DATA TRANSMITTING AND RECEIVING SYSTEM 有权
标题翻译：数据发送和接收系统
公开(公告)号：US20110314349A1
公开(公告)日：2011-12-22
申请号：US13221418
申请日：2011-08-30
申请人： Jung-Bae LEE
发明人： Jung-Bae LEE
IPC分类号： H04L1/18
CPC分类号： H04L1/1671 , H04L1/0025 , H04L25/0272 , H04L25/0278 , H04L25/0288 , H04L25/03038 , H04L25/03057 , H04L25/03885
摘要： A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.
摘要翻译：一种具有发送单元的系统，该发送单元发送由输出数据和相关错误检测码形成的输出数据信号和相应的接收单元。输出数据信号由传输单元中的预加重驱动器预先强调。接收单元包括均衡接收的输出数据信号的均衡器和分析错误检测码的误差检测器，以确定接收数据中是否存在位错误。在连续数据传输故障时，均衡器中的均衡系数或预加重驱动器中的预加重系数被改变。

9. 发明授权

US08050332B2 System and method for selectively performing single-ended and differential signaling 有权
标题翻译：用于选择性地执行单端和差分信号的系统和方法
公开(公告)号：US08050332B2
公开(公告)日：2011-11-01
申请号：US12103823
申请日：2008-04-16
申请人： Hoe-ju Chung , Jung-bae Lee
发明人： Hoe-ju Chung , Jung-bae Lee
IPC分类号： H04B14/06
CPC分类号： H04L25/0264 , H04L25/0272
摘要： In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.
摘要翻译：在通信系统中，使用单端或差分信令有选择地发送数据。相对于具有不同相对相位的多个时钟信号发送数据。当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

10. 发明授权

US07999367B2 Stacked memory device 有权
标题翻译：堆叠式存储设备
公开(公告)号：US07999367B2
公开(公告)日：2011-08-16
申请号：US12123583
申请日：2008-05-20
申请人： Uk-song Kang , Jung-bae Lee , Hoe-ju Chung
发明人： Uk-song Kang , Jung-bae Lee , Hoe-ju Chung
IPC分类号： H01L23/02
CPC分类号： G11C5/025 , G11C5/02 , G11C5/063 , H01L25/0657 , H01L2224/05573 , H01L2224/13025 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2924/00014 , H01L2924/15331 , H01L2224/05599
摘要： A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.
摘要翻译：半导体存储器件包括堆叠的多个插入器芯片，每个插入器芯片放置较小的对应的存储器芯片，其中堆叠的多个插入器芯片中的最下层插入器芯片安装在缓冲芯片上。堆叠的多个插入器芯片中的每一个包括具有连接衬垫对应的存储器件的中心部分和具有多个穿通硅通孔（TSV）的外围部分。堆叠的多个插入器芯片中的相邻插入器芯片的相应多个TSV通过垂直连接元件连接，以形成从相应存储器芯片向缓冲器芯片传送写入数据和从其读取数据的多个内部信号路径。

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