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    • 5. 发明授权
    • Techniques for adjusting clock signals to compensate for noise
    • 调整时钟信号以补偿噪声的技术
    • US09565036B2
    • 2017-02-07
    • US13378024
    • 2010-05-31
    • Jared ZerbePradeep BatraBrian Leibowitz
    • Jared ZerbePradeep BatraBrian Leibowitz
    • H04L7/00H04L25/00H04L25/40H04L25/02G06F1/10H03K5/1252
    • H04L25/0264G06F1/10H03K5/1252
    • A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.
    • 第一集成电路(IC)具有可调延迟电路和第一接口电路。 向可调延迟电路提供第一时钟信号以产生提供给第一接口电路的延迟的时钟信号。 第二IC具有电源电压检测电路和与第一IC传输数据的第二接口电路。 电源电压检测电路向第一IC提供指示第二IC的电源电压中的噪声的噪声信号。 可调节延迟电路根据噪声信号调整延迟的时钟信号的延迟。 在其他实施例中,边缘彩色时钟信号通过使IC间的共同的高频抖动来减少集成电路(IC)之间的数据传输中的高频抖动的影响。 在其他实施例中,电源电压用于在多个IC上产生时钟信号。
    • 9. 发明授权
    • Apparatus and methods for tuning a communication link for power conservation
    • 用于调谐通信链路以进行节能的装置和方法
    • US09419746B1
    • 2016-08-16
    • US14280351
    • 2014-05-16
    • ALTERA CORPORATION
    • Gregg William BaecklerDavid W. Mendel
    • H04L1/00
    • H04L1/0001H04L1/203H04L25/0264H04L25/03031H04L25/03343Y02D50/10
    • The present disclosure provides apparatus and methods for dynamic analog tuning for power reduction. As disclosed herein, the analog controls on a high-speed serial communication channel are dynamically adjusted in a manner so as to either reduce the total system power or move power dissipation between the transmitter and receiver devices, with little or no negative effect to the bit error rate. One embodiment relates to a method for tuning a communication link. The method includes occasionally determining whether the bit error rate for the communication link is acceptably low. Control parameters for analog circuitry of the communication link are adjusted to decrease power used if the bit error rate is acceptably low and are adjusted to increase power used if the bit error rate is not acceptably low. Other embodiments, aspects and features are also disclosed.
    • 本公开提供了用于功率降低的动态模拟调谐的装置和方法。 如本文所公开的,高速串行通信信道上的模拟控制被动态调整,以便降低总系统功率或者在发射机和接收机设备之间移动功率消耗,对该位很少或没有负面影响 错误率。 一个实施例涉及一种用于调谐通信链路的方法。 该方法包括偶尔地确定通信链路的比特错误率是否可接受地低。 调整通信链路的模拟电路的控制参数,以减少误码率可接受的低功耗,如果误码率不可接受,则调整为增加使用的功率。 还公开了其它实施例,方面和特征。