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1. 发明申请

US20110101422A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110101422A1
公开(公告)日：2011-05-05
申请号：US12985636
申请日：2011-01-06
申请人： Kaori AKAMATSU
发明人： Kaori AKAMATSU
IPC分类号： H01L27/092 , H01L29/04
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译：半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

2. 发明授权

US07893501B2 Semiconductor device including MISFET having internal stress film 有权
标题翻译：包括具有内部应力膜的MISFET的半导体器件
公开(公告)号：US07893501B2
公开(公告)日：2011-02-22
申请号：US12170191
申请日：2008-07-09
申请人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
发明人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译：半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

3. 发明授权

US07417289B2 Semiconductor device having internal stress film 有权
标题翻译：具有内部应力膜的半导体器件
公开(公告)号：US07417289B2
公开(公告)日：2008-08-26
申请号：US11730988
申请日：2007-04-05
申请人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
发明人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译：半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

4. 发明授权

US06380585B1 Nonvolatile semiconductor device capable of increased electron injection efficiency 失效
标题翻译：能够提高电子注入效率的非易失性半导体器件
公开(公告)号：US06380585B1
公开(公告)日：2002-04-30
申请号：US09588308
申请日：2000-06-06
申请人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
发明人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L29/42324 , H01L29/7885
摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.
摘要翻译：本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层，形成在远离通道区域的区域中。由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

5. 发明授权

US06358799B2 Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device 失效
标题翻译：非易失性半导体存储器件及其制造方法以及半导体集成电路器件
公开(公告)号：US06358799B2
公开(公告)日：2002-03-19
申请号：US09727536
申请日：2000-12-04
申请人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
发明人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.
摘要翻译：在具有包括第一水平的第一表面区域的表面的半导体衬底中，具有低于第一水平的第二水平的第二表面区域和将第一表面区域和第二表面区域连接在一起的阶梯侧区域，通道区域有三重结构。因此，在台阶侧区域和第二表面区域之间的角部及其附近形成高电场。在第一表面区域也形成高电场。结果，电子注入浮栅的效率大大增加。

6. 发明授权

US6121655A Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit 失效
标题翻译：非易失性半导体存储器件及其制造方法和半导体集成电路
公开(公告)号：US6121655A
公开(公告)日：2000-09-19
申请号：US848
申请日：1997-12-30
申请人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
发明人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L29/66825 , H01L29/42324 , H01L29/7885
摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.
摘要翻译：本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层，形成在远离通道区域的区域中。由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

7. 发明授权

US09159771B2 Organic EL panel and manufacturing method thereof 有权
标题翻译：有机EL面板及其制造方法
公开(公告)号：US09159771B2
公开(公告)日：2015-10-13
申请号：US13982007
申请日：2011-12-02
申请人： Kaori Akamatsu , Seiji Nishiyama
发明人： Kaori Akamatsu , Seiji Nishiyama
IPC分类号： H01L27/32 , H01L51/56 , H01L51/50
CPC分类号： H01L27/32 , H01L27/3246 , H01L51/5088 , H01L51/5096 , H01L51/56
摘要： The present invention is to provide an organic EL panel that is able to prevent the problems resulting from the unnecessary bank residues at a relatively low cost and has excellent light-emitting characteristics and a long life, and manufacturing method of the organic EL panel. Specifically, an organic EL element is obtained by forming organic EL elements by sequentially laminating an anode, a transparent conductive film, a hole-injection layer, a buffer layer, an organic light-emitting layer, a cathode, and a passivation layer on one surface of a substrate. Each bank residue positioned on the surface of the hole-injection layer has a diameter not greater than 0.2 μm in one direction when the substrate is seen in plan view. Preferably, when the substrate is seen in plan view, the area of each bank residue is set to be not greater than 0.4 μm2, or more preferably not greater than 0.04 μm2.
摘要翻译：本发明提供一种有机EL面板，其能够以相对较低的成本防止由于不需要的银屑残留而产生的问题，并且具有优异的发光特性和长寿命，以及有机EL面板的制造方法。具体地说，有机EL元件是通过在阳极，透明导电膜，空穴注入层，缓冲层，有机发光层，阴极和钝化层之间依次层叠而形成有机EL元件而得到的基材表面。当在平面图中看到基板时，位于空穴注入层表面上的每个堤坝残留物在一个方向上具有不大于0.2μm的直径。优选地，当在平面图中看到基板时，每个堤岸残留物的面积被设定为不大于0.4μm2，或更优选地不大于0.04μm2。

8. 发明申请

US20100171415A1 LIGHT-EMITTING DEVICE AND DISPLAY APPARATUS 审中-公开
标题翻译：发光装置和显示装置
公开(公告)号：US20100171415A1
公开(公告)日：2010-07-08
申请号：US12616878
申请日：2009-11-12
申请人： Kaori AKAMATSU , Hidehiro YOSHIDA
发明人： Kaori AKAMATSU , Hidehiro YOSHIDA
IPC分类号： H01L51/54
CPC分类号： H01L51/5012 , H01L27/3246
摘要： A light-emitting device includes a first electrode, a second electrode, a light-emitting layer between the first electrode and the second electrode, and banks that delimit the light-emitting layer. An upper surface of the light-emitting layer has a pair of sloping portions that each slope upward toward a lateral surface of one of the banks. The light-emitting layer is thicker about a lower boundary position than at a center of the light-emitting layer. The boundary position corresponds to an intersection of a lower surface of the light-emitting layer and the lateral surface of one of the banks. A width of each sloping portion is at least approximately 2 μm and at most approximately 10% of a width of the light-emitting layer. Thus, it is possible to obtain a light-emitting device having a long life and having less variation in the luminance and an organic EL display apparatus having such a light-emitting device.
摘要翻译：发光装置包括第一电极，第二电极，第一电极和第二电极之间的发光层以及限定发光层的堤。发光层的上表面具有一对倾斜部分，每一倾斜部分朝向其中一个堤岸的侧表面向上倾斜。发光层比发光层的中心处的下边界位置更厚。边界位置对应于发光层的下表面和一个堤的侧表面的交点。每个倾斜部分的宽度为发光层宽度的至少约2μm至多约10％。因此，可以获得具有长寿命且亮度变化较小的发光器件和具有这种发光器件的有机EL显示装置。

9. 发明授权

US07205615B2 Semiconductor device having internal stress film 有权
标题翻译：具有内部应力膜的半导体器件
公开(公告)号：US07205615B2
公开(公告)日：2007-04-17
申请号：US10859219
申请日：2004-06-03
申请人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
发明人： Masafumi Tsutsui , Hiroyuki Umimoto , Kaori Akamatsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L27/092
摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.
摘要翻译：半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

10. 发明授权

US06184553B2 Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device 失效
公开(公告)号：US06184553B2
公开(公告)日：2001-02-06
申请号：US09325772
申请日：1999-06-04
申请人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
发明人： Shinji Odanaka , Kaori Akamatsu , Junichi Kato , Atsushi Hori , Seiki Ogura
IPC分类号： H07L27115
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

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