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1. 发明申请

US20080277723A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20080277723A1
公开(公告)日：2008-11-13
申请号：US12085669
申请日：2006-11-29
申请人： Yuji Fukui , Kazuhiko Yoshino , Satoshi Hikida , Shuhji Enomoto
发明人： Yuji Fukui , Kazuhiko Yoshino , Satoshi Hikida , Shuhji Enomoto
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7834 , H01L29/41783 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.
摘要翻译：在本发明的一个实施例中，公开了具有包括元件隔离区域的小尺寸的高耐压晶体管。半导体器件设置有形成在半导体衬底上的元件隔离区域; 由元件隔离区域划分的有源区域; 通过在其间具有栅绝缘膜而形成在有源区中的半导体衬底上的栅电极; 布置在所述半导体衬底下面的栅电极下的沟道区; 位于所述栅电极的两侧的源极区域和漏极区域; 以及位于源极区域和漏极区域之间的一个或两个以及沟道区域之间的漂移区域。源极区域和漏极区域中的一个或两个至少部分地位于元件隔离区域上，并且通过漂移区域与沟道区域连接。

2. 发明授权

US07843014B2 Small size transistor semiconductor device capable of withstanding high voltage 有权
标题翻译：能承受高电压的小尺寸晶体管半导体器件
公开(公告)号：US07843014B2
公开(公告)日：2010-11-30
申请号：US12085669
申请日：2006-11-29
申请人： Yuji Fukui , Kazuhiko Yoshino , Satoshi Hikida , Shuhji Enomoto
发明人： Yuji Fukui , Kazuhiko Yoshino , Satoshi Hikida , Shuhji Enomoto
IPC分类号： H01L23/62 , H01L23/48
CPC分类号： H01L29/7834 , H01L29/41783 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.
摘要翻译：在本发明的一个实施例中，公开了具有包括元件隔离区域的小尺寸的高耐压晶体管。半导体器件设置有形成在半导体衬底上的元件隔离区域; 由元件隔离区域划分的有源区域; 通过在其间具有栅绝缘膜而形成在有源区中的半导体衬底上的栅电极; 布置在所述半导体衬底下面的栅电极下的沟道区; 位于所述栅电极的两侧的源极区域和漏极区域; 以及位于源极区域和漏极区域之间的一个或两个以及沟道区域之间的漂移区域。源极区域和漏极区域中的一个或两个至少部分地位于元件隔离区域上，并且通过漂移区域与沟道区域连接。

3. 发明授权

US5198373A Process for fabricating a semiconductor device 失效
标题翻译：制造半导体器件的工艺
公开(公告)号：US5198373A
公开(公告)日：1993-03-30
申请号：US886399
申请日：1992-05-21
申请人： Kazuhiko Yoshino
发明人： Kazuhiko Yoshino
IPC分类号： H01L21/22 , H01L21/265 , H01L21/331 , H01L21/74 , H01L21/761 , H01L29/10 , H01L29/73 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/26506 , H01L29/1004 , Y10S148/01 , Y10S148/011
摘要： A process for fabricating a semiconductor device basically includes forming a boron implanted layer intended to be a base region by implanting boron ions to a substrate through a first opening, implanting fluorine ions to the substrate through a second opening serving to define an emitter-inner base formation region beneath the second opening and in the boron implanted layer to lower the boron ion concentration of that region only thereby lowering the peak carrier concentration of an inner base region than that of an emitter region to be formed later, and doping the region defined by a third opening with arsenic ions to form the emitter region with the inner base region underlying.
摘要翻译：制造半导体器件的工艺基本上包括：通过将第一开口注入硼离子到基片上来形成硼基注入层，所述硼注入层通过第二开口注入到衬底中，所述第二开口用于限定发射极 - 内部基极在第二开口下方和硼注入层中的形成区域，以降低该区域的硼离子浓度，从而降低内部碱性区域的峰值载流子浓度比稍后形成的发射极区域的峰值载流子浓度，并掺杂由具有砷离子的第三个开口以形成底部区域的发射极区域。

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