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1. 发明授权

US08488621B2 Communication network system and error verification method 失效
标题翻译：通信网络系统和错误验证方法
公开(公告)号：US08488621B2
公开(公告)日：2013-07-16
申请号：US11774700
申请日：2007-07-09
申请人： Kazunori Morimoto
发明人： Kazunori Morimoto
IPC分类号： H04L12/43
CPC分类号： H04L12/40013 , H04L12/4035 , H04L12/407 , H04L2012/40241
摘要： At least one node on a network acquires boundary violation information and frame state information concerning a reception slot and adjacent slots. Based on the boundary violation information and frame state information concerning the slots, the node verifies an error factor in the reception slot. Based on verification of the error factor, the node determines that data of a frame received in the reception slot can be used. When determining that the data of the received frame can be used, the node uses the received frame for control.
摘要翻译：网络上的至少一个节点获取关于接收时隙和相邻时隙的边界违例信息和帧状态信息。基于与时隙有关的边界违规信息和帧状态信息，节点验证接收时隙中的误差因子。基于错误因子的验证，节点确定可以使用在接收时隙中接收到的帧的数据。当确定可以使用接收到的帧的数据时，节点使用接收的帧进行控制。

2. 发明授权

US08427170B2 Drive circuit array substrate and production and test methods thereof 有权
标题翻译：驱动电路阵列基板及其制作及试验方法
公开(公告)号：US08427170B2
公开(公告)日：2013-04-23
申请号：US12717272
申请日：2010-03-04
申请人： Kazunori Morimoto , Tsuyoshi Ozaki
发明人： Kazunori Morimoto , Tsuyoshi Ozaki
IPC分类号： G01R31/02
CPC分类号： G09G3/006 , G09G3/325 , G09G2300/0842 , G09G2310/0286 , Y10T29/49169
摘要： A drive circuit array substrate allowing for tests without mounting any driver ICs and without using expensive panel contact jigs and production and test methods thereof are provided. A data voltage application circuit, data selection circuit, gate selection circuit, and anode driver connected to a display pixel forming zone are formed on a drive circuit array substrate. The data voltage application circuit, data selection circuit, gate selection circuit, and anode driver allows for lighting test and aging test of the light emitting elements in the display pixel forming zone and measurement of transistor characteristics without mounting any driver ICs and without using expensive panel contract jigs.
摘要翻译：提供一种驱动电路阵列基板，其允许在不安装任何驱动器IC的情况下进行测试，并且不使用昂贵的面板接触夹具及其制造和测试方法。在驱动电路阵列基板上形成数据电压施加电路，数据选择电路，栅极选择电路以及与显示像素形成区连接的阳极驱动器。数据电压施加电路，数据选择电路，栅极选择电路和阳极驱动器允许在显示像素形成区域中的发光元件的照明测试和老化测试以及晶体管特性的测量而不安装任何驱动器IC并且不使用昂贵的面板契约夹具

3. 发明申请

US20130092927A1 CIRCUIT BOARD, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING CIRCUIT BOARD 有权
标题翻译：电路板，显示装置及制造电路板的方法
公开(公告)号：US20130092927A1
公开(公告)日：2013-04-18
申请号：US13639138
申请日：2011-01-17
申请人： Atsuhito Murai , Shinya Tanaka , Hideki Kitagawa , Hajime Imai , Mitsunori Imade , Tetsuo Kikuchi , Kazunori Morimoto , Junya Shimada , Jun Nishimura
发明人： Atsuhito Murai , Shinya Tanaka , Hideki Kitagawa , Hajime Imai , Mitsunori Imade , Tetsuo Kikuchi , Kazunori Morimoto , Junya Shimada , Jun Nishimura
IPC分类号： H01L27/15
CPC分类号： H01L27/15 , G02F1/13318 , G02F1/13338 , G02F1/136204 , G02F1/1368 , H01L27/1222 , H01L27/1225 , H01L27/1251 , H01L29/42384 , H01L29/78633 , H01L29/7869
摘要： The circuit board (1) of the present invention includes a plurality of transistor elements provided on a single insulating substrate (2) for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT (10) having a channel layer (11) formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT (20) having a channel layer (21) formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT (10) and the a-Si TFT (20) is a bottom-gate transistor.
摘要翻译：本发明的电路板（1）包括设置在单个绝缘基板（2）上的多个晶体管元件，用于各个像素的二维排列或者在一组预定数量的像素中的各个像素。多个晶体管元件中的至少一个是具有由氧化物半导体形成的沟道层（11）的氧化物TFT（10），并且多个晶体管元件中的至少另一个是具有沟道层（21）由例如非晶硅半导体形成。氧化物TFT（10）和a-Si TFT（20）中的每一个都是底栅晶体管。

4. 发明授权

US08411212B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US08411212B2
公开(公告)日：2013-04-02
申请号：US13001644
申请日：2009-05-29
申请人： Dai Chiba , Takehiko Sakai , Tetsuo Fujita , Kazunori Morimoto , Yoshiharu Kataoka , Shogo Nishiwaki
发明人： Dai Chiba , Takehiko Sakai , Tetsuo Fujita , Kazunori Morimoto , Yoshiharu Kataoka , Shogo Nishiwaki
IPC分类号： G02F1/1335
CPC分类号： G06F3/047 , G02F1/13338 , G02F2001/134345 , G06F3/0412
摘要： A touch electrode and a detection element are positioned in at least two of pixels. The touch electrode is formed in a first substrate, and is positioned so as to face a counter electrode. The touch electrode contacts the counter electrode and is electrically connected thereto when a second substrate is pressed and bent toward the first substrate. The detection element is connected to the touch electrode, and detects the electrical connection between the touch electrode and the counter electrode.
摘要翻译：触摸电极和检测元件位于至少两个像素中。触摸电极形成在第一基板中，并且被定位成面对对电极。触摸电极接触对电极，并且当第二基板被按压并朝向第一基板弯曲时与其对应地电连接。检测元件连接到触摸电极，并且检测触摸电极和对电极之间的电连接。

5. 发明申请

US20100225770A1 DRIVE CIRCUIT ARRAY SUBSTRATE AND PRODUCTION AND TEST METHODS THEREOF 有权
标题翻译：驱动电路阵列基板及其生产及测试方法
公开(公告)号：US20100225770A1
公开(公告)日：2010-09-09
申请号：US12717272
申请日：2010-03-04
申请人： Kazunori MORIMOTO , Tsuyoshi Ozaki
发明人： Kazunori MORIMOTO , Tsuyoshi Ozaki
IPC分类号： H04N17/02 , G01R31/02 , H01R43/00
CPC分类号： G09G3/006 , G09G3/325 , G09G2300/0842 , G09G2310/0286 , Y10T29/49169
摘要： A drive circuit array substrate allowing for tests without mounting any driver ICs and without using expensive panel contact jigs and production and test methods thereof are provided.A data voltage application circuit, data selection circuit, gate selection circuit, and anode driver connected to a display pixel forming zone are formed on a drive circuit array substrate. The data voltage application circuit, data selection circuit, gate selection circuit, and anode driver allows for lighting test and aging test of the light emitting elements in the display pixel forming zone and measurement of transistor characteristics without mounting any driver ICs and without using expensive panel contract jigs.
摘要翻译：提供一种驱动电路阵列基板，其允许在不安装任何驱动器IC的情况下进行测试，并且不使用昂贵的面板接触夹具及其制造和测试方法。在驱动电路阵列基板上形成数据电压施加电路，数据选择电路，栅极选择电路以及与显示像素形成区连接的阳极驱动器。数据电压施加电路，数据选择电路，栅极选择电路和阳极驱动器允许在显示像素形成区域中的发光元件的照明测试和老化测试以及晶体管特性的测量而不安装任何驱动器IC并且不使用昂贵的面板契约夹具

6. 发明申请

US20080008209A1 COMMUNICATION NETWORK SYSTEM AND ERROR VERIFICATION METHOD 失效
标题翻译：通信网络系统和错误验证方法
公开(公告)号：US20080008209A1
公开(公告)日：2008-01-10
申请号：US11774700
申请日：2007-07-09
申请人： Kazunori Morimoto
发明人： Kazunori Morimoto
IPC分类号： H04L12/43
CPC分类号： H04L12/40013 , H04L12/4035 , H04L12/407 , H04L2012/40241
摘要： At least one node on a network acquires boundary violation information and frame state information concerning a reception slot and adjacent slots. Based on the boundary violation information and frame state information concerning the slots, the node verifies an error factor in the reception slot. Based on verification of the error factor, the node determines that data of a frame received in the reception slot can be used. When determining that the data of the received frame can be used, the node uses the received frame for control.
摘要翻译：网络上的至少一个节点获取关于接收时隙和相邻时隙的边界违例信息和帧状态信息。基于与时隙有关的边界违规信息和帧状态信息，节点验证接收时隙中的误差因子。基于错误因子的验证，节点确定可以使用在接收时隙中接收到的帧的数据。当确定可以使用接收到的帧的数据时，节点使用接收的帧进行控制。

7. 发明申请

US20080008103A1 COMMUNICATION NETWORK SYSTEM AND WAKEUP METHOD FOR UN-WAKEUP NODE 有权
标题翻译：通信网络系统和唤醒方法
公开(公告)号：US20080008103A1
公开(公告)日：2008-01-10
申请号：US11774694
申请日：2007-07-09
申请人： Atsuya Suzuki , Kazunori Morimoto
发明人： Atsuya Suzuki , Kazunori Morimoto
IPC分类号： H04J1/16
CPC分类号： H04L12/403 , H04L12/12 , H04L12/40169 , H04L2012/40241 , H04L2012/40273 , Y02D50/40
摘要： A vehicular network communication apparatus and method detects and wakes up a sleeping network node through transmission of a pseudo-wakeup signal after an initial wake up fails for one or more nodes in the network.
摘要翻译：车辆网络通信装置和方法通过在网络中的一个或多个节点的初始唤醒失败之后通过发送伪唤醒信号来检测和唤醒睡眠网络节点。

8. 外观设计

USD429595S Microwave oven 失效
公开(公告)号：USD429595S
公开(公告)日：2000-08-22
申请号：US110352
申请日：1999-09-01
申请人： Yasunori Kusachi , Kensaku Noda , Kazunori Morimoto , Satoru Fujio , Noriyuki Mori
设计人： Yasunori Kusachi , Kensaku Noda , Kazunori Morimoto , Satoru Fujio , Noriyuki Mori

9. 发明授权

US09111810B2 Circuit board and display device including first and second channel layers made of different semiconductor materials 有权
标题翻译：电路板和显示装置，包括由不同半导体材料制成的第一和第二通道层
公开(公告)号：US09111810B2
公开(公告)日：2015-08-18
申请号：US13643652
申请日：2011-03-02
申请人： Hideki Kitagawa , Shinya Tanaka , Hajime Imai , Atsuhito Murai , Mitsunori Imade , Tetsuo Kikuchi , Kazunori Morimoto , Junya Shimada , Jun Nishimura
发明人： Hideki Kitagawa , Shinya Tanaka , Hajime Imai , Atsuhito Murai , Mitsunori Imade , Tetsuo Kikuchi , Kazunori Morimoto , Junya Shimada , Jun Nishimura
IPC分类号： H01L29/10 , H01L29/12 , H01L27/12 , H01L27/146 , H01L27/144
CPC分类号： H01L27/1251 , H01L27/1225 , H01L27/1259 , H01L27/1446 , H01L27/14632 , H01L27/14678
摘要： A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.
摘要翻译：电路板（1）在绝缘基板（2）上包括多个晶体管元件。多个晶体管元件中的至少一个是氧化物TFT（10），其包括作为沟道层（11）的氧化物半导体。多个晶体管元件中的至少一个是与作为电路元件的功能的氧化物TFT（10）不同的a-SiTFT（20）（i），（ii）包括作为沟道层（21）的无定形硅半导体。氧化物TFT（10）是顶栅晶体管，并且a-SiTFT（20）是底栅晶体管。这提供：一种配置，其可以（a）增强配备有作为电路部件的各自功能不同的TFT的电路板的性能，（b）减小安装TFT所需的面积; 以及电路基板的制造方法。

10. 发明申请

US20130214279A1 CIRCUIT BOARD AND DISPLAY DEVICE 审中-公开
标题翻译：电路板和显示设备
公开(公告)号：US20130214279A1
公开(公告)日：2013-08-22
申请号：US13695082
申请日：2011-02-23
申请人： Jun Nishimura , Hideki Kitagawa , Atsuhito Murai , Hajime Imai , Shinya Tanaka , Mitsunori Imade , Tetsuo Kikuchi , Junya Shimada , Kazunori Morimoto
发明人： Jun Nishimura , Hideki Kitagawa , Atsuhito Murai , Hajime Imai , Shinya Tanaka , Mitsunori Imade , Tetsuo Kikuchi , Junya Shimada , Kazunori Morimoto
IPC分类号： H01L27/02
CPC分类号： H01L29/78663 , G02F1/13338 , G02F1/13624 , G06F3/0412 , H01L27/0207 , H01L27/0705 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L29/78633 , H01L29/7869
摘要： A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.
摘要翻译：氧化物TFT元件（3）的源极和漏极电极层（3s / 3d）由第一导电层形成。氧化物TFT元件（3）的栅极（3g）和a-Si TFT元件（5）的栅电极（5g）由单个导电层即第二导电层形成。 a-Si TFT元件（5）的源极和漏极电极层（5s / 5d）由第三导电层形成。第三导电层形成在第二导电层上方的厚度方向上，其中每个导电层堆叠在绝缘基板（2）上。此外，第一导电层在厚度方向上形成在第二导电层的下方。因此，可以提供可以使形成在绝缘基板上的晶体管元件的集成度提高的电路板。

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