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1. 发明授权

US08822432B2 Equol production accelerating composition 有权
标题翻译： Equol生产加速组成
公开(公告)号：US08822432B2
公开(公告)日：2014-09-02
申请号：US12304301
申请日：2007-06-15
申请人： Kenichi Oe , Takashi Kimura
发明人： Kenichi Oe , Takashi Kimura
IPC分类号： C07H3/04 , A61K31/7016 , A61K31/7012
CPC分类号： C07H3/04 , A23K20/105 , A23L33/10 , A61K31/7012 , A61K31/7016 , A61K31/7032
摘要： A composition which can significantly accelerate equol production is provided. When formulated in a pharmaceutical preparation or a food or drink, this composition exerts effects of preventing a vascular disease by the cholesterol lowering function, preventing breast cancer or prostatic cancer, and preventing and/or treating osteoporosis. Also, when formulated in a feed or a pet food, the bone density is enhanced, so that it exerts effects to prevent weak legs of a pig, to strengthen egg shell of a laying hen, to prevent osteoporosis in a dog etc., and the like. It is a composition which comprises lactobionic acid, a salt of lactobionic acid or lactobionolactone as an active ingredient and a food or drink, a feed, a pet food or a pharmaceutical preparation, which contains the composition, and have effects to prevent and treat osteoporosis, an function to increase bone density, an effect to prevent breast cancer or prostatic cancer, and a cholesterol lowering function.
摘要翻译：提供了可显着加速牛尿酚生产的组合物。当配制在药物制剂或食品或饮料中时，该组合物通过胆固醇降低功能，预防乳腺癌或前列腺癌，以及预防和/或治疗骨质疏松症具有预防血管疾病的作用。此外，当配制在饲料或宠物食品中时，骨密度增强，从而发挥防止猪腿的作用，加强产蛋鸡的蛋壳，以防止狗等中的骨质疏松症，以及类似。它是包含乳糖酸，乳糖酸或乳糖内酯的盐作为活性成分的组合物和含有该组合物的食品或饮料，饲料，宠物食品或药物制剂，并具有预防和治疗骨质疏松症的作用，增加骨密度的功能，预防乳腺癌或前列腺癌的作用和降低胆固醇的功能。

2. 发明申请

US20090233880A1 EQUOL PRODUCTION ACCELERATING COMPOSITION 有权
标题翻译：均质生产加速组合物
公开(公告)号：US20090233880A1
公开(公告)日：2009-09-17
申请号：US12304301
申请日：2007-06-15
申请人： Kenichi Oe , Takashi Kimura
发明人： Kenichi Oe , Takashi Kimura
IPC分类号： A61K31/7032 , C07C59/10 , C07H3/04 , A61K31/19 , A61P19/00 , A61P35/00 , A61P9/00
CPC分类号： C07H3/04 , A23K20/105 , A23L33/10 , A61K31/7012 , A61K31/7016 , A61K31/7032
摘要： A composition which can significantly accelerate equol production is provided. When formulated in a pharmaceutical preparation or a food or drink, this composition exerts effects of preventing a vascular disease by the cholesterol lowering function, preventing breast cancer or prostatic cancer, and preventing and/or treating osteoporosis. Also, when formulated in a feed or a pet food, the bone density is enhanced, so that it exerts effects to prevent weak legs of a pig, to strengthen egg shell of a laying hen, to prevent osteoporosis in a dog etc., and the like. It is a composition which comprises lactobionic acid, a salt of lactobionic acid or lactobionolactone as an active ingredient and a food or drink, a feed, a pet food or a pharmaceutical preparation, which contains the composition, and have effects to prevent and treat osteoporosis, an function to increase bone density, an effect to prevent breast cancer or prostatic cancer, and a cholesterol lowering function.
摘要翻译：提供了可显着加速牛尿酚生产的组合物。当配制在药物制剂或食品或饮料中时，该组合物通过胆固醇降低功能，预防乳腺癌或前列腺癌，以及预防和/或治疗骨质疏松症具有预防血管疾病的作用。此外，当配制在饲料或宠物食品中时，骨密度增强，从而发挥防止猪腿的作用，加强产蛋鸡的蛋壳，以防止狗等中的骨质疏松症，以及类似。它是包含乳糖酸，乳糖酸或乳糖内酯的盐作为活性成分的组合物和含有该组合物的食品或饮料，饲料，宠物食品或药物制剂，并具有预防和治疗骨质疏松症的作用，增加骨密度的功能，预防乳腺癌或前列腺癌的作用和降低胆固醇的功能。

3. 发明授权

US07948407B2 High-speed serial interface circuit and electronic instrument 有权
标题翻译：高速串行接口电路和电子仪器
公开(公告)号：US07948407B2
公开(公告)日：2011-05-24
申请号：US12649677
申请日：2009-12-30
申请人： Takemi Yonezawa , Kenichi Oe
发明人： Takemi Yonezawa , Kenichi Oe
IPC分类号： H03M9/00
CPC分类号： H04L7/0008 , H04L7/0337
摘要： A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage. The present invention can prevent a partial characteristic variation by NBTI by inputting a free-running clock into a logic block, and operating it.
摘要翻译：高速串行接口电路包括数据接收器电路，时钟信号接收器电路，至少包括串行/并行转换电路的逻辑电路块，自由运行的时钟信号产生电路，时钟信号检测电路和输出屏蔽电路。时钟信号检测电路将来自时钟信号接收器电路的接收时钟信号与自由运行时钟信号发生电路的自由运行时钟信号进行比较，以检测时钟信号是否通过差分时钟信号线传输。当时钟信号检测电路检测到时钟信号不通过差分时钟信号线传送时，输出屏蔽电路屏蔽来自逻辑电路块的输出信号，使得输出信号不被传送到后级的电路。本发明可以通过将自由运行的时钟输入到逻辑块中来防止NBTI的部分特性变化并进行操作。

4. 发明授权

US07663515B2 High-speed serial interface circuit and electronic instrument 失效
标题翻译：高速串行接口电路和电子仪器
公开(公告)号：US07663515B2
公开(公告)日：2010-02-16
申请号：US12196553
申请日：2008-08-22
申请人： Takemi Yonezawa , Kenichi Oe
发明人： Takemi Yonezawa , Kenichi Oe
IPC分类号： H03M9/00
CPC分类号： H04L7/0008 , H04L7/0337
摘要： A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage. The present invention can prevent a partial characteristic variation by NBTI by inputting a free-running clock into a logic block, and operating it.
摘要翻译：高速串行接口电路包括数据接收器电路，时钟信号接收器电路，至少包括串行/并行转换电路的逻辑电路块，自由运行的时钟信号产生电路，时钟信号检测电路和输出屏蔽电路。时钟信号检测电路将来自时钟信号接收器电路的接收时钟信号与自由运行时钟信号发生电路的自由运行时钟信号进行比较，以检测时钟信号是否通过差分时钟信号线传输。当时钟信号检测电路检测到时钟信号不通过差分时钟信号线传送时，输出屏蔽电路屏蔽来自逻辑电路块的输出信号，使得输出信号不被传送到后级的电路。本发明可以通过将自由运行的时钟输入到逻辑块中来防止NBTI的部分特性变化并进行操作。

5. 发明申请

US20100103002A1 HIGH-SPEED SERIAL INTERFACE CIRCUIT AND ELECTRONIC INSTRUMENT 有权
标题翻译：高速串行接口电路和电子仪器
公开(公告)号：US20100103002A1
公开(公告)日：2010-04-29
申请号：US12649677
申请日：2009-12-30
申请人： Takemi YONEZAWA , Kenichi OE
发明人： Takemi YONEZAWA , Kenichi OE
IPC分类号： H03M9/00
CPC分类号： H04L7/0008 , H04L7/0337
摘要： A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage. The present invention can prevent a partial characteristic variation by NBTI by inputting a free-running clock into a logic block, and operating it.
摘要翻译：高速串行接口电路包括数据接收器电路，时钟信号接收器电路，至少包括串行/并行转换电路的逻辑电路块，自由运行的时钟信号产生电路，时钟信号检测电路和输出屏蔽电路。时钟信号检测电路将来自时钟信号接收器电路的接收时钟信号与自由运行时钟信号发生电路的自由运行时钟信号进行比较，以检测时钟信号是否通过差分时钟信号线传输。当时钟信号检测电路检测到时钟信号不通过差分时钟信号线传送时，输出屏蔽电路屏蔽来自逻辑电路块的输出信号，使得输出信号不被传送到后级的电路。本发明可以通过将自由运行的时钟输入到逻辑块中来防止NBTI的部分特性变化并进行操作。

6. 发明申请

US20090066546A1 HIGH-SPEED SERIAL INTERFACE CIRCUIT AND ELECTRONIC INSTRUMENT 失效
标题翻译：高速串行接口电路和电子仪器
公开(公告)号：US20090066546A1
公开(公告)日：2009-03-12
申请号：US12196553
申请日：2008-08-22
申请人： Takemi YONEZAWA , Kenichi OE
发明人： Takemi YONEZAWA , Kenichi OE
IPC分类号： H03M9/00
CPC分类号： H04L7/0008 , H04L7/0337
摘要： A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage. The present invention can prevent a partial characteristic variation by NBTI by inputting a free-running clock into a logic block, and operating it.
摘要翻译：高速串行接口电路包括数据接收器电路，时钟信号接收器电路，至少包括串行/并行转换电路的逻辑电路块，自由运行的时钟信号产生电路，时钟信号检测电路和输出屏蔽电路。时钟信号检测电路将来自时钟信号接收器电路的接收时钟信号与自由运行时钟信号发生电路的自由运行时钟信号进行比较，以检测时钟信号是否通过差分时钟信号线传输。当时钟信号检测电路检测到时钟信号不通过差分时钟信号线传送时，输出屏蔽电路屏蔽来自逻辑电路块的输出信号，使得输出信号不被传送到后级的电路。本发明可以通过将自由运行的时钟输入到逻辑块中来防止NBTI的部分特性变化并进行操作。

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