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1. 发明申请

US20100080210A1 System clock synchronization apparatus and method for mobile communication system 有权
标题翻译：用于移动通信系统的系统时钟同步装置和方法
公开(公告)号：US20100080210A1
公开(公告)日：2010-04-01
申请号：US12586762
申请日：2009-09-28
申请人： Keun Bok Kim
发明人： Keun Bok Kim
IPC分类号： H04J3/06
CPC分类号： H04J3/0685 , G06F1/12 , H03L7/06 , H03L7/095 , H04W56/00
摘要： A system clock synchronization apparatus, for use in a mobile communication system, supplies a GPS clock received from a GPS reception module to a Radio Frequency clock generation module and selects a candidate system clock. The candidate system clock is selected from among plural candidate system clocks having different phases, which can be most stably synchronized with a reference synchronization time signal as the final system clock. The apparatus includes a Global Positioning System reception module; a Radio Frequency clock generation module that generates a system reference clock and outputs an RF clock generated by synchronizing the system reference clock to the GPS clock in phase; and a system clock generation module that generates multiple candidate system clocks having different phases using the RF clock and selects one of the candidate system clocks which generates in a range of an enable duration of the reference synchronization time signal.
摘要翻译：用于移动通信系统的系统时钟同步装置将从GPS接收模块接收的GPS时钟提供给射频时钟生成模块，并选择候选系统时钟。从具有不同相位的多个候选系统时钟中选择候选系统时钟，其可以与作为最终系统时钟的参考同步时间信号最稳定地同步。该装置包括一个全球定位系统接收模块; 射频时钟生成模块，其生成系统参考时钟，并输出通过将系统参考时钟同步到GPS时钟而产生的RF时钟; 以及系统时钟生成模块，其使用所述RF时钟生成具有不同相位的多个候选系统时钟，并且选择在所述参考同步时间信号的使能持续时间的范围内生成的候选系统时钟之一。

2. 发明授权

US08108626B2 Apparatus and method of time keeping for non-real-time operating system 有权
标题翻译：非实时操作系统的时间设备和方法
公开(公告)号：US08108626B2
公开(公告)日：2012-01-31
申请号：US11960184
申请日：2007-12-19
申请人： Keun-Bok Kim , Kyu-Il Yeon
发明人： Keun-Bok Kim , Kyu-Il Yeon
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/00
CPC分类号： G06F1/14
摘要： An apparatus and method of time keeping for a non-real-time OS is provided. The apparatus includes a processor and a Field Programmable Gate Array (FPGA). The processor requests performance of a Dual-Port Random Access Memory (DPRAM) read/write (R/W) operation in a DPRAM R/W time interval in a Time Division Multiple Access (TDMA) scheme using a system clock. Upon receipt of the DPRAM R/W operation performance request from the processor, the FPGA compares the operation performance request time with an access time table defining a DPRAM R/W time interval for each processor, generated in the TDMA scheme using the system clock. The FPGA performs the operation requested by the processor when the operation performance request has been made in the DPRAM R/W time interval of the processor.
摘要翻译：提供了一种用于非实时操作系统的时间保持装置和方法。该装置包括处理器和现场可编程门阵列（FPGA）。处理器使用系统时钟在时分多址（TDMA）方案中在DPRAM R / W时间间隔中请求执行双端口随机存取存储器（DPRAM）读/写（R / W）操作。在从处理器接收到DPRAM R / W操作性能请求时，FPGA将操作性能请求时间与使用系统时钟在TDMA方案中生成的每个处理器定义DPRAM R / W时间间隔的访问时间表进行比较。当在处理器的DPRAM R / W时间间隔内进行操作性能请求时，FPGA执行处理器请求的操作。

3. 发明授权

US08599825B2 System clock synchronization apparatus and method for mobile communication system 有权
标题翻译：用于移动通信系统的系统时钟同步装置和方法
公开(公告)号：US08599825B2
公开(公告)日：2013-12-03
申请号：US12586762
申请日：2009-09-28
申请人： Keun Bok Kim
发明人： Keun Bok Kim
IPC分类号： H04J3/06 , H04B7/19
CPC分类号： H04J3/0685 , G06F1/12 , H03L7/06 , H03L7/095 , H04W56/00
摘要： A system clock synchronization apparatus, for use in a mobile communication system, supplies a GPS clock received from a GPS reception module to a Radio Frequency clock generation module and selects a candidate system clock. The candidate system clock is selected from among plural candidate system clocks having different phases, which can be most stably synchronized with a reference synchronization time signal as the final system clock. The apparatus includes a Global Positioning System reception module; a Radio Frequency clock generation module that generates a system reference clock and outputs an RF clock generated by synchronizing the system reference clock to the GPS clock in phase; and a system clock generation module that generates multiple candidate system clocks having different phases using the RF clock and selects one of the candidate system clocks which generates in a range of an enable duration of the reference synchronization time signal.
摘要翻译：用于移动通信系统的系统时钟同步装置将从GPS接收模块接收的GPS时钟提供给射频时钟生成模块，并选择候选系统时钟。候选系统时钟从具有不同相位的多个候选系统时钟中选择，其可以与作为最终系统时钟的参考同步时间信号最稳定地同步。该装置包括一个全球定位系统接收模块; 射频时钟生成模块，其生成系统参考时钟，并输出通过将系统参考时钟同步到GPS时钟而产生的RF时钟; 以及系统时钟生成模块，其使用所述RF时钟生成具有不同相位的多个候选系统时钟，并且选择在所述参考同步时间信号的使能持续时间的范围内生成的候选系统时钟之一。

4. 发明授权

US08514800B2 Method for transmitting and receiving ethernet data between digital unit and RF unit and apparatus thereof 有权
标题翻译：用于在数字单元和RF单元之间发送和接收以太网数据的方法及其装置
公开(公告)号：US08514800B2
公开(公告)日：2013-08-20
申请号：US13009353
申请日：2011-01-19
申请人： Keun-Bok Kim , Chang-Won Kim , Han-Ul Moon , Chang-Won Choi
发明人： Keun-Bok Kim , Chang-Won Kim , Han-Ul Moon , Chang-Won Choi
IPC分类号： H04W4/00
CPC分类号： H04W88/085 , H04W80/02
摘要： A method for transmitting Ethernet data in a Digital Unit (DU) that processes a baseband and interfaces with at least two Radio Frequency (RF) Units (RUs) is provided. The method includes setting location information of two or more Ethernet channels in a first subchannel of a radio frame, allocating the two or more Ethernet channels in second subchannels of the radio frame, using the location information, and transmitting the radio frame to the at least two RUs.
摘要翻译：提供了一种在处理基带并与至少两个射频（RF）单元（RU））接口的数字单元（DU）中发送以太网数据的方法。该方法包括：在无线帧的第一子信道中设置两个或多个以太网信道的位置信息，使用位置信息在无线帧的第二子信道中分配两个或多个以太网信道，并且至少向两个RU。

5. 发明授权

US08037335B2 Apparatus and method for synchronizing a channel card in a mobile communication system 有权
标题翻译：用于在移动通信系统中同步信道卡的设备和方法
公开(公告)号：US08037335B2
公开(公告)日：2011-10-11
申请号：US12048393
申请日：2008-03-14
申请人： Keun-Bok Kim , Seock-Kyu Kim
发明人： Keun-Bok Kim , Seock-Kyu Kim
IPC分类号： G06F1/12 , H04L7/00 , H03M13/00
CPC分类号： H04J3/0685
摘要： An apparatus and a method for synchronization in a channel card in a mobile communication system are provided. A channel card for synchronizing a Digital Signal Processing (DSP) modem and a system clock in a mobile communication system includes the DSP modem for sending a reference signal, informing of a start of a transmission, to a Field-Programmable Gate Array (FPGA) modem, and the FPGA modem for comparing a reception time of the reference signal with a Global Positioning System (GPS) timer, for recording a GPS timer value corresponding to a start point based on the comparison, and for sending to the DSP modem the recorded GPS timer value corresponding to the start point at a preset GPS timer reference time.
摘要翻译：提供了一种移动通信系统中的信道卡同步的装置和方法。用于同步数字信号处理（DSP）调制解调器和移动通信系统中的系统时钟的通道卡包括用于向现场可编程门阵列（FPGA）发送参考信号（通知开始传输）的DSP调制解调器，调制解调器和用于将参考信号的接收时间与全球定位系统（GPS）定时器进行比较的FPGA调制解调器，用于基于比较记录与起始点相对应的GPS定时器值，并且用于向DSP调制解调器发送所记录的 GPS定时器值对应于预设GPS定时器参考时间的起点。

6. 发明申请

US20110182255A1 METHOD FOR TRANSMITTING AND RECEIVING ETHERNET DATA BETWEEN DIGITAL UNIT AND RF UNIT AND APPARATUS THEREOF 有权
标题翻译：用于发送和接收数字单元和RF单元之间的以太网数据的方法及其装置
公开(公告)号：US20110182255A1
公开(公告)日：2011-07-28
申请号：US13009353
申请日：2011-01-19
申请人： Keun-Bok KIM , Chang-Won KIM , Han-Ul MOON , Chang-Won CHOI
发明人： Keun-Bok KIM , Chang-Won KIM , Han-Ul MOON , Chang-Won CHOI
IPC分类号： H04W4/00
CPC分类号： H04W88/085 , H04W80/02
摘要： A method for transmitting Ethernet data in a Digital Unit (DU) that processes a baseband and interfaces with at least two Radio Frequency (RF) Units (RUs) is provided. The method includes setting location information of two or more Ethernet channels in a first subchannel of a radio frame, allocating the two or more Ethernet channels in second subchannels of the radio frame, using the location information, and transmitting the radio frame to the at least two RUs.
摘要翻译：提供了一种在处理基带并与至少两个射频（RF）单元（RU））接口的数字单元（DU）中发送以太网数据的方法。该方法包括：在无线帧的第一子信道中设置两个或多个以太网信道的位置信息，使用位置信息在无线帧的第二子信道中分配两个或多个以太网信道，并且至少向两个RU。

7. 发明申请

US20080226005A1 APPARATUS AND METHOD FOR SYNCHRONIZING A CHANNEL CARD IN A MOBILE COMMUNICATION SYSTEM 有权
标题翻译：用于在移动通信系统中同步通道卡的装置和方法
公开(公告)号：US20080226005A1
公开(公告)日：2008-09-18
申请号：US12048393
申请日：2008-03-14
申请人： Keun-Bok KIM , Seock-Kyu KIM
发明人： Keun-Bok KIM , Seock-Kyu KIM
IPC分类号： H04L7/00
CPC分类号： H04J3/0685
摘要： An apparatus and a method for synchronization in a channel card in a mobile communication system are provided. A channel card for synchronizing a Digital Signal Processing (DSP) modem and a system clock in a mobile communication system includes the DSP modem for sending a reference signal, informing of a start of a transmission, to a Field-Programmable Gate Array (FPGA) modem, and the FPGA modem for comparing a reception time of the reference signal with a Global Positioning System (GPS) timer, for recording a GPS timer value corresponding to a start point based on the comparison, and for sending to the DSP modem the recorded GPS timer value corresponding to the start point at a preset GPS timer reference time.
摘要翻译：提供了一种移动通信系统中的信道卡同步的装置和方法。用于同步数字信号处理（DSP）调制解调器和移动通信系统中的系统时钟的通道卡包括用于向现场可编程门阵列（FPGA）发送参考信号（通知开始传输）的DSP调制解调器，调制解调器和用于将参考信号的接收时间与全球定位系统（GPS）定时器进行比较的FPGA调制解调器，用于基于比较记录与起始点相对应的GPS定时器值，并且用于向DSP调制解调器发送所记录的 GPS定时器值对应于预设GPS定时器参考时间的起点。

8. 发明申请

US20080148087A1 APPARATUS AND METHOD OF TIME KEEPING FOR NON-REAL-TIME OPERATING SYSTEM 有权
标题翻译：非实时操作系统的时间保持装置和方法
公开(公告)号：US20080148087A1
公开(公告)日：2008-06-19
申请号：US11960184
申请日：2007-12-19
申请人： Keun-Bok KIM , Kyu-II Yeon
发明人： Keun-Bok KIM , Kyu-II Yeon
IPC分类号： G06F1/14
CPC分类号： G06F1/14
摘要： An apparatus and method of time keeping for a non-real-time OS is provided. The apparatus includes a processor and a Field Programmable Gate Array (FPGA). The processor requests performance of a Dual-Port Random Access Memory (DPRAM) read/write (R/W) operation in a DPRAM R/W time interval in a Time Division Multiple Access (TDMA) scheme using a system clock. Upon receipt of the DPRAM R/W operation performance request from the processor, the FPGA compares the operation performance request time with an access time table defining a DPRAM R/W time interval for each processor, generated in the TDMA scheme using the system clock. The FPGA performs the operation requested by the processor when the operation performance request has been made in the DPRAM R/W time interval of the processor.
摘要翻译：提供了一种用于非实时操作系统的时间保持装置和方法。该装置包括处理器和现场可编程门阵列（FPGA）。处理器使用系统时钟在时分多址（TDMA）方案中在DPRAM R / W时间间隔中请求执行双端口随机存取存储器（DPRAM）读/写（R / W）操作。在从处理器接收到DPRAM R / W操作性能请求时，FPGA将操作性能请求时间与使用系统时钟在TDMA方案中生成的每个处理器定义DPRAM R / W时间间隔的访问时间表进行比较。当在处理器的DPRAM R / W时间间隔内进行操作性能请求时，FPGA执行处理器请求的操作。

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