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1. 发明授权

US08079004B2 Efficient exhaustive path-based static timing analysis using a fast estimation technique 有权
标题翻译：使用快速估计技术的高效穷举路径静态时序分析
公开(公告)号：US08079004B2
公开(公告)日：2011-12-13
申请号：US12433203
申请日：2009-04-30
申请人： Cristian Soviani , Rachid N. Helaihel , Khalid Rahmat
发明人： Cristian Soviani , Rachid N. Helaihel , Khalid Rahmat
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/84
摘要： One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information. If so, the system then performs an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path. Otherwise, the system computes a path-based delay for the path by performing a path-based STA on the path.
摘要翻译：本发明的一个实施例提供一种在电路设计中执行有效的基于路径的静态时序分析（STA）的系统。在操作期间，系统识别电路设计内的一组路径，其中每个路径包括一个或多个段。对于路径集合中的路径，系统确定路径中的至少一个段是否与先前通过执行基于路径的STA计算的不同路径共享，其中不同路径中的至少一个段相关联与先前计算的基于路径的定时信息。如果是这样，则系统至少基于与不同路径中的共享段相关联的基于路径的定时信息，对路径的基于路径的延迟进行估计。否则，系统通过在路径上执行基于路径的STA来计算路径的基于路径的延迟。

2. 发明申请

US20120278778A1 Clock-Reconvergence Pessimism Removal In Hierarchical Static Timing Analysis 有权
标题翻译：时钟 - 再现缓和悲观消除在分层静态时序分析
公开(公告)号：US20120278778A1
公开(公告)日：2012-11-01
申请号：US13095713
申请日：2011-04-27
申请人： Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar
发明人： Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5031 , G06F2217/62 , G06F2217/84
摘要： A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.
摘要翻译：公开了用于在分级静态时序分析（HSTA）期间执行时钟再收敛悲观消除（CRPR）的系统和方法。时钟网络被分成多个块。顶层包括不包括在多个块中的时钟组件。执行块级分析以确定多个块中的每一个的定时信息。如果可用，在块级分析中考虑来自顶级分析的CRPR数据。随后，对包含在顶级分析中的组件执行类似的分析。如果可用，来自底层分析的CRPR数据在顶级分析中被考虑。可以从其他级别的分析级别请求CRPR数据。重复这些步骤直到分析完成。

3. 发明授权

US07366997B1 Methods and apparatuses for thermal analysis based circuit design 有权
标题翻译：基于热分析的电路设计方法与装置
公开(公告)号：US07366997B1
公开(公告)日：2008-04-29
申请号：US11034391
申请日：2005-01-11
申请人： Khalid Rahmat , Kenneth S. McElvain
发明人： Khalid Rahmat , Kenneth S. McElvain
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5036 , G06F2217/16
摘要： Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the present invention reduces the power dissipation and improves the timing of an integrated circuit to optimize the design. A thermal analysis is used to determine the temperature dependent power dissipation of a circuit and the temperature distribution of the circuit resulting from dissipating the heat created by the temperature dependent power dissipation. Then, the components of the design are selectively transformed to reduce the power dissipation and to improve timing based on the temperature solution. The transformation may include placement changes and netlist changes, such as the change of transistor threshold voltages for cells or for blocks of the circuit chip.
摘要翻译：用于减少功率使用的电路设计的方法和装置，例如降低依赖于温度的功率使用，和/或改善定时，例如降低温度依赖性延迟或转换时间。本发明的至少一个实施例降低了功率消耗，并且改善了集成电路的定时以优化设计。热分析用于确定电路的与温度有关的功耗以及由于温度依赖功耗而产生的散热所导致的电路温度分布。然后，选择性地转换设计的部件以降低功耗并且基于温度解决方案来改进定时。该变换可以包括位置变化和网表变化，例如电池或电路芯片块的晶体管阈值电压的变化。

4. 发明授权

US08572535B2 Thermal analysis based circuit design 有权
标题翻译：基于热分析的电路设计
公开(公告)号：US08572535B2
公开(公告)日：2013-10-29
申请号：US13099329
申请日：2011-05-02
申请人： Khalid Rahmat , Kenneth S. McElvain
发明人： Khalid Rahmat , Kenneth S. McElvain
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5036 , G06F2217/16
摘要： Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the present invention reduces the power dissipation and improves the timing of an integrated circuit to optimize the design. A thermal analysis is used to determine the temperature dependent power dissipation of a circuit and the temperature distribution of the circuit resulting from dissipating the heat created by the temperature dependent power dissipation. Then, the components of the design are selectively transformed to reduce the power dissipation and to improve timing based on the temperature solution. The transformation may include placement changes and netlist changes, such as the change of transistor threshold voltages for cells or for blocks of the circuit chip.
摘要翻译：用于减少功率使用的电路设计的方法和装置，例如降低依赖于温度的功率使用，和/或改善定时，例如降低温度依赖性延迟或转换时间。本发明的至少一个实施例降低了功率消耗，并且改善了集成电路的定时以优化设计。热分析用于确定电路的与温度有关的功耗以及由于温度依赖功耗而产生的散热所导致的电路温度分布。然后，选择性地转换设计的部件以降低功耗并且基于温度解决方案来改进定时。该变换可以包括位置变化和网表变化，例如电池或电路芯片块的晶体管阈值电压的变化。

5. 发明申请

US20130246991A1 Clock-Reconvergence Pessimism Removal In Hierarchical Static Timing Analysis 有权
标题翻译：时钟 - 再现缓和悲观消除在分层静态时序分析
公开(公告)号：US20130246991A1
公开(公告)日：2013-09-19
申请号：US13873026
申请日：2013-04-29
申请人： Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar
发明人： Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5031 , G06F2217/62 , G06F2217/84
摘要： A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.
摘要翻译：公开了用于在分级静态时序分析（HSTA）期间执行时钟再收敛悲观消除（CRPR）的系统和方法。时钟网络被分成多个块。顶层包括不包括在多个块中的时钟组件。执行块级分析以确定多个块中的每一个的定时信息。如果可用，在块级分析中考虑来自顶级分析的CRPR数据。随后，对包含在顶级分析中的组件执行类似的分析。如果可用，来自底层分析的CRPR数据在顶级分析中被考虑。可以从其他级别的分析级别请求CRPR数据。重复这些步骤直到分析完成。

6. 发明授权

US08434040B2 Clock-reconvergence pessimism removal in hierarchical static timing analysis 有权
标题翻译：在分层静态时序分析中的时钟再聚合悲观消除
公开(公告)号：US08434040B2
公开(公告)日：2013-04-30
申请号：US13095713
申请日：2011-04-27
申请人： Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar
发明人： Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5031 , G06F2217/62 , G06F2217/84
摘要： A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.
摘要翻译：公开了用于在分级静态时序分析（HSTA）期间执行时钟再收敛悲观消除（CRPR）的系统和方法。时钟网络被分成多个块。顶层包括不包括在多个块中的时钟组件。执行块级分析以确定多个块中的每一个的定时信息。如果可用，在块级分析中考虑来自顶级分析的CRPR数据。随后，对包含在顶级分析中的组件执行类似的分析。如果可用，来自底层分析的CRPR数据在顶级分析中被考虑。可以从其他级别的分析级别请求CRPR数据。重复这些步骤直到分析完成。

7. 发明申请

US20120078605A1 Methods and Apparatuses for Circuit Simulation 审中-公开
标题翻译：电路仿真的方法和装置
公开(公告)号：US20120078605A1
公开(公告)日：2012-03-29
申请号：US13301759
申请日：2011-11-21
申请人： Khalid Rahmat , Ming Huei Young
发明人： Khalid Rahmat , Ming Huei Young
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment, a method comprising identifying a sub-network of the linear circuit, the sub-network having one or more internal nodes, one or more interface nodes, and branches connecting the one or more internal nodes and the one or more interface nodes, the sub-network having at least one of a capacitor and an inductor, is described. The method in one embodiment comprises determining a linear equation system for transient simulation of the linear circuit, the linear equation system containing no variable representing the one or more internal nodes.
摘要翻译：在一个实施例中，一种方法包括识别线性电路的子网络，具有一个或多个内部节点的子网络，一个或多个接口节点以及连接一个或多个内部节点和一个或多个接口节点的分支描述了具有电容器和电感器中的至少一个的子网络。一个实施例中的方法包括确定用于线性电路的瞬态仿真的线性方程组，线性方程组不包含表示一个或多个内部节点的变量。

8. 发明授权

US07278120B2 Methods and apparatuses for transient analyses of circuits 有权
标题翻译：电路瞬态分析的方法和装置
公开(公告)号：US07278120B2
公开(公告)日：2007-10-02
申请号：US10897459
申请日：2004-07-23
申请人： Khalid Rahmat , Kenneth S. McElvain
发明人： Khalid Rahmat , Kenneth S. McElvain
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/78
摘要： Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic approach to represent the cell group so that the probability of a more severe waveform for the current of the cell group is under a certain level. For example, the cells in a group are partitioned as switching cells and non-switching cells using cell toggle rates for the determination of the time varying current. The circuit model of the power supply network includes the current sources according to the estimated time varying currents for the cell groups, the power supply wire resistance, the power supply to ground wire capacitance, well capacitance and the de-coupling capacitance from non-switching cells.
摘要翻译：使用分层方法对电路进行瞬态分析的方法和装置。在一个实施例中，根据平均功耗，电池在电源网络上局部分组。使用概率方法估计每个小区组的时变电流，以表示小区组，使得小区组的当前电流的更严重波形的概率在一定水平以下。例如，使用单元切换速率将组中的单元划分为切换单元和非切换单元，以确定时变电流。电源网络的电路模型包括根据电池组的估计时变电流的电流源，电源线电阻，接地线电容的电源，阱电容和非开关的去耦电容细胞。

9. 发明申请

US20060031795A1 Methods and apparatuses for transient analyses of circuits 有权
公开(公告)号：US20060031795A1
公开(公告)日：2006-02-09
申请号：US10897459
申请日：2004-07-23
申请人： Khalid Rahmat , Kenneth McElvain
发明人： Khalid Rahmat , Kenneth McElvain
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/78
摘要： Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic approach to represent the cell group so that the probability of a more severe waveform for the current of the cell group is under a certain level. For example, the cells in a group are partitioned as switching cells and non-switching cells using cell toggle rates for the determination of the time varying current. The circuit model of the power supply network includes the current sources according to the estimated time varying currents for the cell groups, the power supply wire resistance, the power supply to ground wire capacitance, well capacitance and the de-coupling capacitance from non-switching cells.

10. 发明授权

US08775855B2 Reducing memory used to store totals in static timing analysis 有权
标题翻译：减少用于在静态时序分析中存储总计的内存
公开(公告)号：US08775855B2
公开(公告)日：2014-07-08
申请号：US13095719
申请日：2011-04-27
申请人： Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar , Rachid Helaihel
发明人： Sarvesh Bhardwaj , Khalid Rahmat , Kayhan Kucukcakar , Rachid Helaihel
IPC分类号： G06F1/00
CPC分类号： G06F1/10
摘要： A system and a method are disclosed for reducing memory used in storing totals during static timing analysis. Totals are stored at various points along paths analyzed in static timing analysis. Some totals may not be merged for reasons including differing clock re-convergence pessimism removal (CRPR) dominators, exceptions, or clocks. Totals at a point may be stored in a super-tag mapping table and replaced at the point with a super-tag. The super-tag includes a super-tag ID referencing the totals stored in the super-tag mapping table. The super-tag also includes a time delay value. The time delay value allows the super-tag ID to be reused in other super-tags at other points while still storing total time delays at the other points. Therefore, the memory used to store totals is reduced in many situations.
摘要翻译：公开了一种用于在静态时序分析期间减少用于存储总计的存储器的系统和方法。总计存储在静态时序分析中分析的路径上的各个点处。一些总计可能不会被合并，原因包括不同的时钟再收敛悲观消除（CRPR）主导者，例外或时钟。某一点的总计可以存储在超级标签映射表中，并在具有超级标签的点上替换。超级标签包括引用存储在超级标签映射表中的总计的超级标签ID。超级标签还包括时间延迟值。时间延迟值允许超级标签ID在其他点的其他超级标签中重新使用，同时仍然在其他点存储总时间延迟。因此，在许多情况下，用于存储总计的内存减少了。

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