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1. 发明申请

US20100243731A1 DATA CARRIER AND DATA CARRIER SYSTEM 失效
标题翻译：数据载体和数据载体系统
公开(公告)号：US20100243731A1
公开(公告)日：2010-09-30
申请号：US12439128
申请日：2007-08-30
申请人： Kikuzo Sawada , Yoshikazu Sugawara , Takashi Kubo
发明人： Kikuzo Sawada , Yoshikazu Sugawara , Takashi Kubo
IPC分类号： G06K5/00 , G06K19/067
CPC分类号： G07C9/00039 , G06K19/0723
摘要： A region to store authentication commands to perform authentication between a data carrier and a reader/writer device is divided into at least three areas, and as for the three areas, a first authentication command is stored in a first area, a second authentication command is stored in a second area, and a third authentication command is stored in a third area, and security levels can be selected depending on a command of an inquiry signal (41) transmitted from a reader/writer device (10), and thereby selection of the security level suitable for circumstances can be realized by a simple constitution.
摘要翻译：用于存储用于在数据载体和读取/写入器设备之间执行认证的认证命令的区域被划分为至少三个区域，并且对于三个区域，第一认证命令被存储在第一区域中，第二认证命令是存储在第二区域中，并且第三认证命令被存储在第三区域中，并且可以根据从读取器/写入器设备（10）发送的查询信号（41）的命令来选择安全级别，从而选择适合情况的安全级别可以通过简单的构成来实现。

2. 发明授权

US07102422B1 Semiconductor booster circuit having cascaded MOS transistors 失效
标题翻译：具有级联MOS晶体管的半导体升压电路
公开(公告)号：US07102422B1
公开(公告)日：2006-09-05
申请号：US08423089
申请日：1995-04-18
申请人： Kikuzo Sawada , Yoshikazu Sugawara
发明人： Kikuzo Sawada , Yoshikazu Sugawara
IPC分类号： G05F3/02
CPC分类号： H02M3/073 , H02M2003/075 , H02M2003/076 , H02M2003/078
摘要： The semiconductor booster circuit includes a plurality of stages, each of which has a MOS transistor and two capacitors. The MOS transistor, having a drain, a source and a gate, is formed in a well of a substrate portion. One capacitor has a terminal connected to the drain of the MOS transistor, while the other capacitor has a terminal connected to the gate of the MOS transistor. A first clock signal generating means generate a first clock signal via another terminal of one capacitor. A second clock signal generating mean s generate a second clock signal, with a larger amplitude than a power supply voltage, via another terminal of another capacitor. The plurality of stages are cascaded together, and in each of the stages the source of the MOS transistor is electrically connected to the well in which the transistor is formed, while the wells are electrically insulated from each other.
摘要翻译：半导体升压电路包括多个级，其中每一级具有MOS晶体管和两个电容器。具有漏极，源极和栅极的MOS晶体管形成在衬底部分的阱中。一个电容器具有连接到MOS晶体管的漏极的端子，而另一个电容器具有连接到MOS晶体管的栅极的端子。第一时钟信号发生装置经由一个电容器的另一个端子产生第一时钟信号。第二时钟信号产生装置s通过另一个电容器的另一端产生具有比电源电压更大的振幅的第二时钟信号。多个级级联在一起，并且在每个级中，MOS晶体管的源极电连接到形成晶体管的阱，而阱彼此电绝缘。

3. 发明授权

US5557572A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5557572A
公开(公告)日：1996-09-17
申请号：US307251
申请日：1994-09-16
申请人： Kikuzo Sawada , Hiroshi Mawatari
发明人： Kikuzo Sawada , Hiroshi Mawatari
IPC分类号： G11C16/10 , G11C16/16 , G11C7/00 , G11C11/34
CPC分类号： G11C16/10 , G11C16/16
摘要： An electrically alterable non-volatile semiconductor memory device includes a plurality of electrically alterable memory cells arranged in columns and rows, a decoder circuit which selects at least one of the plurality of memory cells and does not select others, a writing circuit for writing a selected data in the selected memory cell through the decoder circuit, a reading circuit for reading a data stored in the selected memory cell through the decoder circuit, a comparing circuit for holding the data stored in the selected memory cell and data to be written in the memory cell and comparing both the data with each other, a judging circuit for judging whether the stored data in the selected memory cell is required to be altered or not on the basis of the comparison result of the comparing circuit, and an alteration control circuit for performing altering of the data of the memory cell when stored data is required to be altered on the basis of the judgment result of the judging circuit.
摘要翻译：一种电可更改的非易失性半导体存储器件包括以列和行排列的多个电可更改的存储单元，选择多个存储单元中的至少一个并且不选择其它存储单元的解码器电路，用于写入所选择的写入电路通过解码器电路在所选择的存储单元中的数据，用于通过解码器电路读取存储在所选存储单元中的数据的读取电路，用于保存存储在所选存储单元中的数据和要写入存储器的数据的比较电路并且比较两个数据;判断电路，用于根据比较电路的比较结果来判断所选择的存储单元中存储的数据是否需要改变;以及变更控制电路，用于执行当存储数据需要根据判断电路的判断结果进行改变时，更改存储器单元的数据。

4. 发明授权

US5514994A Bootstrap circuit 失效
标题翻译：自举电路
公开(公告)号：US5514994A
公开(公告)日：1996-05-07
申请号：US525344
申请日：1995-09-07
申请人： Kikuzo Sawada
发明人： Kikuzo Sawada
IPC分类号： G11C11/407 , G11C16/06 , G11C17/00 , H01L21/822 , H01L27/04 , H02M3/07 , H03K19/017 , H03K19/094 , H03K17/16
CPC分类号： H03K19/01714 , H02M3/07
摘要： A bootstrap circuit particularly suitable for low voltage applications and use with semiconductor memories is disclosed.
摘要翻译：公开了一种特别适用于低电压应用并与半导体存储器一起使用的自举电路。

5. 发明授权

US5491656A Non-volatile semiconductor memory device and a method of using the same 失效
标题翻译：非挥发性半导体存储器件及其使用方法
公开(公告)号：US5491656A
公开(公告)日：1996-02-13
申请号：US231684
申请日：1994-04-25
申请人： Kikuzo Sawada
发明人： Kikuzo Sawada
IPC分类号： G11C16/10 , G11C16/16 , G11C11/34
CPC分类号： G11C16/16 , G11C16/10
摘要： An electrically alterable non-volatile semiconductor memory. The memory cells are formed in a matrix of columns and rows. A row decoder and column decoder are provided to select one of the row lines and column lines. Mode selection means are provided for selecting a writing mode, a first erasing mode for erasing a row of memory cells, a second erasing mode for erasing a selected memory cell on a bit basis, and a reading mode for reading the contents of each memory cell. The individual erasing modes reduce the overall power consumption of the device, while permitting block erasing as well as individual cell erasing.
摘要翻译：电可变非易失性半导体存储器。存储单元以列和行的矩阵形成。提供行解码器和列解码器以选择行线和列线之一。模式选择装置被提供用于选择写入模式，用于擦除一行存储单元的第一擦除模式，用于以位为单位擦除所选择的存储单元的第二擦除模式和用于读取每个存储单元的内容的读取模式。单独的擦除模式降低了设备的总体功耗，同时允许块擦除以及单独的单元擦除。

6. 发明申请

US20060262589A1 Semiconductor integrated circuit, operating method thereof, and ic card including the circuit 失效
标题翻译：半导体集成电路，其操作方法以及包含该电路的IC卡
公开(公告)号：US20060262589A1
公开(公告)日：2006-11-23
申请号：US10555964
申请日：2004-12-07
申请人： Tadahiko Hirai , Kikuzo Sawada
发明人： Tadahiko Hirai , Kikuzo Sawada
IPC分类号： G11C17/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0014 , G11C17/16 , G11C17/165 , G11C2213/34 , G11C2213/76 , G11C2213/79 , H01L27/101 , H01L27/105 , H01L27/283
摘要： One main electrode of a TFT is connected with one terminal of a two-terminal type nonvolatile memory element, a gate electrode of the TFT is connected with a word line, and the other main electrode thereof is connected with a bit line. The other terminal of the memory element is connected with a base line. A fixed resistor is connected between a connecting point between the other main electrode of the TFT and the bit line and an input terminal of the bit line. In information writing for changing the memory element whose initial state is a low impedance state to a high impedance state, voltages having polarities reverse relative to a reference voltage are applied to the input terminal of the bit line and an input terminal of the base line, respectively, so that a high voltage necessary to change the state is applied between both the terminals of the memory element.
摘要翻译： TFT的一个主电极与两端型非易失性存储元件的一个端子连接，TFT的栅电极与字线连接，而另一个主电极与位线连接。存储元件的另一个端子与基线连接。在TFT的另一个主电极和位线之间的连接点和位线的输入端子之间连接一个固定电阻器。在将初始状态为低阻抗状态的存储元件改变为高阻抗状态的信息写入中，具有相对于参考电压相反极性的电压被施加到位线的输入端和基线的输入端，从而在存储元件的两个端子之间施加改变状态所需的高电压。

7. 发明申请

US20060132288A1 Method of reading information from RF tag and method of writing information therein 审中-公开
标题翻译：从RF标签读取信息的方法及其中写入信息的方法
公开(公告)号：US20060132288A1
公开(公告)日：2006-06-22
申请号：US11286640
申请日：2005-11-23
申请人： Tadahiko Hirai , Keiichi Murai , Kikuzo Sawada
发明人： Tadahiko Hirai , Keiichi Murai , Kikuzo Sawada
IPC分类号： H04Q5/22
CPC分类号： G06K19/0723
摘要： A method of reading information from and writing information onto an RF tag that resonates by electromagnetic inductance, the RF tag including at least two sets of electromagnetic resonance circuits having mutually different resonance frequencies, the at least two sets of electromagnetic resonance circuits having at least one of a resistor and a capacitor, a fuse or antifuse element capable of selecting a low impedance state and a high impedance state on the basis of an electrical signal, and a coil antenna, is provided.
摘要翻译：一种从RF电磁感应谐振的RF标签上读取信息并将信息写入RF标签的方法，所述RF标签包括至少两组谐振频率相互不同的电磁谐振电路，所述至少两组电磁谐振电路具有至少一个电阻器和电容器，能够基于电信号选择低阻抗状态和高阻抗状态的熔丝或反熔丝元件以及线圈天线。

8. 发明授权

US5412601A Non-volatile semiconductor memory device capable of storing multi-value data in each memory cell 失效
标题翻译：能够在每个存储单元中存储多值数据的非易失性半导体存储器件
公开(公告)号：US5412601A
公开(公告)日：1995-05-02
申请号：US112997
申请日：1993-08-30
申请人： Kikuzo Sawada , Toshio Wada
发明人： Kikuzo Sawada , Toshio Wada
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C19/00 , G11C2211/5642 , G11C8/04
摘要： An electrically erasable non-volatile semiconductor memory device comprising a plurality of row lines and column lines, a plurality of memory cells connected in a matrix to the plurality of row lines and column lines, a selection circuit for selecting a desired one of the plurality of memory cells, and write-control circuit for writing data into the plurality of memory cells. The write-control circuit is adapted to preset at least four voltage signals having different voltage values, and to select one of four voltage signals according to a data signal externally applied thereto and applying the selected voltage signal to the selected memory cell. Also included is read-control circuit for reading out data written into the selected memory cell and converting the data read-out from the selected memory cell into a data signal corresponding to one of the four voltage signals.
摘要翻译：一种电可擦除非易失性半导体存储器件，包括多条行线和列线，多个存储单元，以矩阵方式连接到多条行线和列线;选择电路，用于选择多条行存储单元和用于将数据写入多个存储单元的写控制电路。写入控制电路适于预置具有不同电压值的至少四个电压信号，并且根据从外部施加的数据信号选择四个电压信号中的一个，并将所选择的电压信号施加到所选存储单元。还包括用于读出写入所选择的存储单元中的数据并将从所选存储单元读出的数据转换成与四个电压信号之一相对应的数据信号的读控制电路。

9. 发明授权

US5151906A Semiconductor memory device having self-correcting function 失效
标题翻译：具有自我修正功能的半导体存储器件
公开(公告)号：US5151906A
公开(公告)日：1992-09-29
申请号：US517694
申请日：1990-05-02
申请人： Kikuzo Sawada
发明人： Kikuzo Sawada
IPC分类号： G11C29/00 , G06F11/10 , G11C16/06 , G11C17/00 , G11C29/42
CPC分类号： G06F11/1008 , G06F11/1076 , G06F2201/81
摘要： A semiconductor memory device having a self-correcting function comprises memory cells for storing data and memory cells for storing parity bit data. The criterion of detecting in the first read circuit is set smaller and the criterion of detecting in the second read circuit is set greater in value than the current value read in such a state that the electric charge in the memory cell becomes depleted. In this way, the first read circuit detects a current value smaller and the second read circuit detects a current value greater than the value of the current flowing through the memory cell holding the bit error because of charge depletion. Consequently, even if the variation of the threshold resulting from the charge depletion allows the presence of a faulty memory cell, one of the read circuits can make a correct data read.

10. 发明授权

US6000843A Electrically alterable nonvolatile semiconductor memory 失效
标题翻译：电可变非易失性半导体存储器
公开(公告)号：US6000843A
公开(公告)日：1999-12-14
申请号：US813300
申请日：1997-03-10
申请人： Kikuzo Sawada
发明人： Kikuzo Sawada
IPC分类号： G06F11/00 , G11C16/34 , G11C29/50
CPC分类号： G11C16/3495 , G06F11/008 , G11C16/349 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C16/04 , G11C2029/5004
摘要： An electrically alterable nonvolatile semiconductor memory device has a first memory array including a plurality of first memory cells and a second memory array including at least one second memory cell, wherein contents of the first memory array and contents of the second memory array are capable of being altered independently of each other and variation of a specific quality of each second memory cell due to altering of the contents of the second memory cell is examined, in order to estimate the life of the first memory array.
摘要翻译：电可变非易失性半导体存储器件具有包括多个第一存储器单元的第一存储器阵列和包括至少一个第二存储单元的第二存储器阵列，其中第一存储器阵列的内容和第二存储器阵列的内容能够被检查彼此独立地改变，并且检查由于第二存储器单元的内容的改变引起的每个第二存储单元的特定质量的变化，以便估计第一存储器阵列的寿命。

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