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1. 发明申请

US20110281208A1 Hybrid Multi-Layer Mask 有权
标题翻译：混合多层面膜
公开(公告)号：US20110281208A1
公开(公告)日：2011-11-17
申请号：US13188347
申请日：2011-07-21
申请人： Feng-Lung Lin , Kuan-Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
发明人： Feng-Lung Lin , Kuan-Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
IPC分类号： H01L21/77 , G03F1/14 , G03F7/20
CPC分类号： G03F1/00
摘要： A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.
摘要翻译：公开了一种用于暴露半导体衬底上的多个层以形成集成电路器件的混合掩模组。混合掩模集合包括用于多个层的第一子集的一个或多个多层掩模（MLM）的第一组。每个MLM包括用于不同层的多个不同图像，该图像被相对较宽的图像间隔物隔开。混合掩模集合还包括用于多个层的第二子集的第一组一个或多个生产就绪掩模。每个生产就绪掩模包括用于公共层的多个相似图像，每个图像由相对狭窄的划线路分隔开。

2. 发明授权

US08007966B2 Multiple technology node mask 有权
标题翻译：多技术节点掩码
公开(公告)号：US08007966B2
公开(公告)日：2011-08-30
申请号：US13007048
申请日：2011-01-14
申请人： Feng Lung Lin , Kuan Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
发明人： Feng Lung Lin , Kuan Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
IPC分类号： G03F1/00 , G03F7/00
CPC分类号： G03F1/00
摘要： A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern.
摘要翻译：提供了一种制造掩模组的方法。该方法包括提供与多个掩模层相关联的掩模数据。掩模数据包括与第一技术节点相关联的第一模式和与第二技术节点相关联的第二模式。该方法继续确定以形成多个掩模层中的第一掩模层的多技术节点掩码（MTM）。形成第一掩模层的MTM，其包括与第一图案相关联的特征和与第二图案相关联的特征。

3. 发明授权

US08202681B2 Hybrid multi-layer mask 有权
标题翻译：混合多层面膜
公开(公告)号：US08202681B2
公开(公告)日：2012-06-19
申请号：US13188347
申请日：2011-07-21
申请人： Feng-Lung Lin , Kuan-Liang Wu , Che-Rong Liang , Fei-Gwo Tsai
发明人： Feng-Lung Lin , Kuan-Liang Wu , Che-Rong Liang , Fei-Gwo Tsai
IPC分类号： G03F7/00 , G03F1/00
CPC分类号： G03F1/00
摘要： A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.
摘要翻译：公开了一种用于暴露半导体衬底上的多个层以形成集成电路器件的混合掩模组。混合掩模集合包括用于多个层的第一子集的一个或多个多层掩模（MLM）的第一组。每个MLM包括用于不同层的多个不同图像，该图像被相对较宽的图像间隔物隔开。混合掩模集合还包括用于多个层的第二子集的第一组一个或多个生产就绪掩模。每个生产就绪掩模包括用于公共层的多个相似图像，每个图像由相对狭窄的划线路分隔开。

4. 发明授权

US07904855B2 Methods for partially removing circuit patterns from a multi-project wafer 有权
标题翻译：从多工程晶圆部分去除电路图案的方法
公开(公告)号：US07904855B2
公开(公告)日：2011-03-08
申请号：US11536927
申请日：2006-09-29
申请人： Yi-Hong Tseng , Kuan-Liang Wu
发明人： Yi-Hong Tseng , Kuan-Liang Wu
IPC分类号： G06F17/50 , H01L21/00
CPC分类号： H01L21/67282 , B23K26/14 , B23K26/40 , B23K2103/50 , G03F7/70425 , G03F7/70433 , H01L21/67294 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are a method and a system for partially removing circuit patterns from a multi-project wafer. This method and this system can be used to provide a multi-project-wafer to a user without disclosing proprietary circuit information of other customers. At least one integrated circuit design of a user is identified from a plurality of integrated circuit designs of a plurality of users. Those unidentified circuits can be totally removed through circuit removing method. Then the modified multi-project wafer can be delivered to the user without concerns about disclosing information of unidentified circuits which belongs to other customers. In one embodiment, a laser system may be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits. In another embodiment, a diamond-blade saw may also be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits.
摘要翻译：公开了一种从多工程晶片部分去除电路图案的方法和系统。该方法和该系统可以用于向用户提供多工程晶圆，而不会公开其他客户的专有电路信息。从多个用户的多个集成电路设计中识别用户的至少一个集成电路设计。那些不明的电路可以通过电路去除方法完全去除。然后，修改后的多项目晶片可以传递给用户，而不用担心公开属于其他客户的不明电路的信息。在一个实施例中，可以使用激光系统来完全去除未识别的集成电路设计，而不会影响识别的电路的电路性能。在另一个实施例中，金刚石锯片锯也可以用于完全去除未识别的集成电路设计，而不会影响识别的电路的电路性能。

5. 发明授权

US07875406B2 Multiple technology node mask 有权
标题翻译：多技术节点掩码
公开(公告)号：US07875406B2
公开(公告)日：2011-01-25
申请号：US12056897
申请日：2008-03-27
申请人： Feng Lung Lin , Kuan Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
发明人： Feng Lung Lin , Kuan Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
IPC分类号： G03F1/00 , G03C5/00 , H01L21/00
CPC分类号： G03F1/00
摘要： A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main node and the second technology node a sub-node. A mask set including an MTM may also include single technology node masks (STMs) for mask layers in which the first technology node and second technology node and/or the patterns associated with each are not compatible. A single mask set including MTM and STMs, may be used to produce a plurality of devices, each on a different wafer.
摘要翻译：提供了多技术节点掩码（MTM）。 MTM包括与第一技术节点相关联的模式和与第二技术节点相关联的模式。第一技术节点和第二技术节点可能不同。例如，第一技术节点可以是主节点，而第二技术节点可以是子节点。包括MTM的掩模集还可以包括用于掩模层的单技术节点掩码（STM），其中第一技术节点和第二技术节点和/或与每个技术节点相关联的模式不兼容。可以使用包括MTM和STM的单个掩模组来产生多个设备，每个设备在不同的晶片上。

6. 发明申请

US20090246975A1 MULTIPLE TECHNOLOGY NODE MASK 有权
标题翻译：多技术节点掩码
公开(公告)号：US20090246975A1
公开(公告)日：2009-10-01
申请号：US12056897
申请日：2008-03-27
申请人： Feng Lung Lin , Kuan Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
发明人： Feng Lung Lin , Kuan Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
IPC分类号： H01L21/00 , G03F7/00
CPC分类号： G03F1/00
摘要： A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main node and the second technology node a sub-node. A mask set including an MTM may also include single technology node masks (STMs) for mask layers in which the first technology node and second technology node and/or the patterns associated with each are not compatible. A single mask set including MTM and STMs, may be used to produce a plurality of devices, each on a different wafer.
摘要翻译：提供了多技术节点掩码（MTM）。 MTM包括与第一技术节点相关联的模式和与第二技术节点相关联的模式。第一技术节点和第二技术节点可能不同。例如，第一技术节点可以是主节点，而第二技术节点可以是子节点。包括MTM的掩模集还可以包括用于掩模层的单技术节点掩码（STM），其中第一技术节点和第二技术节点和/或与每个技术节点相关联的模式不兼容。可以使用包括MTM和STM的单个掩模组来产生多个设备，每个设备在不同的晶片上。

7. 发明申请

US20110113389A1 MULTIPLE TECHNOLOGY NODE MASK 有权
标题翻译：多技术节点掩码
公开(公告)号：US20110113389A1
公开(公告)日：2011-05-12
申请号：US13007048
申请日：2011-01-14
申请人： Feng Lung Lin , Kuan Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
发明人： Feng Lung Lin , Kuan Liang Wu , Fei-Gwo Tsai , Che-Rong Liang
IPC分类号： G06F17/50
CPC分类号： G03F1/00
摘要： A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern.
摘要翻译：提供了一种制造掩模组的方法。该方法包括提供与多个掩模层相关联的掩模数据。掩模数据包括与第一技术节点相关联的第一模式和与第二技术节点相关联的第二模式。该方法继续确定以形成多个掩模层中的第一掩模层的多技术节点掩码（MTM）。形成第一掩模层的MTM，其包括与第一图案相关联的特征和与第二图案相关联的特征。

8. 发明申请

US20100047698A1 HYBRID MULTI-LAYER MASK 有权
标题翻译：混合多层面膜
公开(公告)号：US20100047698A1
公开(公告)日：2010-02-25
申请号：US12250338
申请日：2008-10-13
申请人： Feng-Lung Lin , Kuan-Liang Wu , Che-Rong Liang , Fei-Gwo Tsai
发明人： Feng-Lung Lin , Kuan-Liang Wu , Che-Rong Liang , Fei-Gwo Tsai
IPC分类号： G03F1/14 , H01L21/027 , G03F7/20
CPC分类号： G03F1/00
摘要： A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.
摘要翻译：公开了一种用于暴露半导体衬底上的多个层以形成集成电路器件的混合掩模组。混合掩模集合包括用于多个层的第一子集的一个或多个多层掩模（MLM）的第一组。每个MLM包括用于不同层的多个不同图像，该图像被相对较宽的图像间隔物隔开。混合掩模集合还包括用于多个层的第二子集的第一组一个或多个生产就绪掩模。每个生产就绪掩模包括用于公共层的多个相似图像，每个图像由相对狭窄的划线路分隔开。

9. 发明授权

US08003281B2 Hybrid multi-layer mask 有权
标题翻译：混合多层面膜
公开(公告)号：US08003281B2
公开(公告)日：2011-08-23
申请号：US12250338
申请日：2008-10-13
申请人： Feng-Lung Lin , Kuan-Liang Wu , Che-Rong Liang , Fei-Gwo Tsai
发明人： Feng-Lung Lin , Kuan-Liang Wu , Che-Rong Liang , Fei-Gwo Tsai
IPC分类号： G03F1/00
CPC分类号： G03F1/00
摘要： A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.
摘要翻译：公开了一种用于暴露半导体衬底上的多个层以形成集成电路器件的混合掩模组。混合掩模集合包括用于多个层的第一子集的一个或多个多层掩模（MLM）的第一组。每个MLM包括用于不同层的多个不同图像，该图像被相对较宽的图像间隔物隔开。混合掩模集合还包括用于多个层的第二子集的第一组一个或多个生产就绪掩模。每个生产就绪掩模包括用于公共层的多个相似图像，每个图像由相对狭窄的划线路分隔开。

10. 发明申请

US20070264798A1 Method and System for Partially Removing Circuit Patterns From a Multi-Project Wafer 有权
标题翻译：从多工程晶圆部分去除电路图案的方法和系统
公开(公告)号：US20070264798A1
公开(公告)日：2007-11-15
申请号：US11536927
申请日：2006-09-29
申请人： Yi-Hong Tseng , Kuan-Liang Wu
发明人： Yi-Hong Tseng , Kuan-Liang Wu
IPC分类号： H01L21/00
CPC分类号： H01L21/67282 , B23K26/14 , B23K26/40 , B23K2103/50 , G03F7/70425 , G03F7/70433 , H01L21/67294 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are a method and a system for partially removing circuit patterns from a multi-project wafer. This method and this system can be used to provide a multi-project-wafer to a user without disclosing proprietary circuit information of other customers. At least one integrated circuit design of a user is identified from a plurality of integrated circuit designs of a plurality of users. Those unidentified circuits can be totally removed through circuit removing method. Then the modified multi-project wafer can be delivered to the user without concerns about disclosing information of unidentified circuits which belongs to other customers. In one embodiment, a laser system may be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits. In another embodiment, a diamond-blade saw may also be used to totally remove the unidentified integrated circuit designs without impacting the circuit performance of identified circuits.
摘要翻译：公开了一种从多工程晶片部分去除电路图案的方法和系统。该方法和该系统可以用于向用户提供多工程晶圆，而不会公开其他客户的专有电路信息。从多个用户的多个集成电路设计中识别用户的至少一个集成电路设计。那些不明的电路可以通过电路去除方法完全去除。然后，修改后的多项目晶片可以传递给用户，而不用担心公开属于其他客户的不明电路的信息。在一个实施例中，可以使用激光系统来完全去除未识别的集成电路设计，而不会影响识别的电路的电路性能。在另一个实施例中，金刚石锯片锯也可用于完全去除未识别的集成电路设计，而不会影响识别的电路的电路性能。

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