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1. 发明授权

US09165968B2 3D-stacked backside illuminated image sensor and method of making the same 有权
标题翻译： 3D叠层背面照明图像传感器及其制作方法
公开(公告)号：US09165968B2
公开(公告)日：2015-10-20
申请号：US13616850
申请日：2012-09-14
申请人： Calvin Yi-Ping Chao , Kuo-Yu Chou , Fu-Lung Hsueh
发明人： Calvin Yi-Ping Chao , Kuo-Yu Chou , Fu-Lung Hsueh
IPC分类号： H01L27/146 , H04N5/374
CPC分类号： H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14641 , H04N5/374
摘要： A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.
摘要翻译：提供一种堆叠式图像传感器及其制造方法。堆叠图像传感器包括其上具有像素阵列的上部芯片。第二芯片包括与像素阵列的列和行相关联的多个列电路和行电路，并且被布置在多个组中的各个列电路和行电路区域中。在每个芯片上形成芯片间接合焊盘。在一个实施例中，第二芯片上的芯片间接合焊盘被线性布置并且被包含在列电路区域和行电路区域内。在其他实施例中，芯片间接合焊盘相对于彼此交错。在一些实施例中，像素阵列的行和列包括多个信号线，并且相应的列电路区域和行电路区域还包括多个芯片间接合焊盘。

2. 发明申请

US20140077057A1 3D-STACKED BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MAKING THE SAME 有权
标题翻译： 3D堆叠式背光照明图像传感器及其制作方法
公开(公告)号：US20140077057A1
公开(公告)日：2014-03-20
申请号：US13616850
申请日：2012-09-14
申请人： Calvin Yi-Ping CHAO , Kuo-Yu CHOU , Fu-Lung HSUEH
发明人： Calvin Yi-Ping CHAO , Kuo-Yu CHOU , Fu-Lung HSUEH
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14641 , H04N5/374
摘要： A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.
摘要翻译：提供一种堆叠式图像传感器及其制造方法。堆叠图像传感器包括其上具有像素阵列的上部芯片。第二芯片包括与像素阵列的列和行相关联的多个列电路和行电路，并且被布置在多个组中的各个列电路和行电路区域中。在每个芯片上形成芯片间接合焊盘。在一个实施例中，第二芯片上的芯片间接合焊盘被线性布置并且被包含在列电路区域和行电路区域内。在其他实施例中，芯片间接合焊盘相对于彼此交错。在一些实施例中，像素阵列的行和列包括多个信号线，并且相应的列电路区域和行电路区域还包括多个芯片间接合焊盘。

3. 发明授权

US08138804B2 Correlated double sampling circuit 失效
标题翻译：相关双采样电路
公开(公告)号：US08138804B2
公开(公告)日：2012-03-20
申请号：US12534840
申请日：2009-08-03
申请人： Kuo-Yu Chou
发明人： Kuo-Yu Chou
IPC分类号： G11C27/02
CPC分类号： H04N5/378 , H04N5/3575
摘要： A correlated double sampling (CDS) circuit for sampling first and second pixel signals, which are respectively transmitted via first and second data lines, in a pixel array. The CDS circuit includes first and second sampling circuits, an amplifier circuit and a control circuit. The control circuit controls the first sampling circuit to sample a reset level and a data level of the first pixel signal in a first sampling period, and controls the second sampling circuit to sample a reset level and a data level of the second pixel signal in a second sampling period. The control circuit controls the amplifier circuit to output the reset level and the data level of the first pixel signal in a first output period, and output the reset level and the data level of the second pixel signal in a second output period.
摘要翻译：用于对通过第一和第二数据线分别在像素阵列中发送的第一和第二像素信号进行采样的相关双采样（CDS）电路。 CDS电路包括第一和第二采样电路，放大器电路和控制电路。所述控制电路控制所述第一采样电路在第一采样周期中对所述第一像素信号的复位电平和数据电平进行采样，并且控制所述第二采样电路对所述第二像素信号的复位电平和数据电平进行采样第二抽样期。控制电路控制放大器电路在第一输出周期中输出复位电平和第一像素信号的数据电平，并在第二输出周期中输出第二像素信号的复位电平和数据电平。

4. 发明申请

US20080252364A1 Reference Voltage Generator for Analog-To-Digital Converter Circuit 有权
标题翻译：用于模数转换器电路的参考电压发生器
公开(公告)号：US20080252364A1
公开(公告)日：2008-10-16
申请号：US11855142
申请日：2007-09-13
申请人： Kuo-Yu Chou
发明人： Kuo-Yu Chou
IPC分类号： G05F1/10
CPC分类号： G05F3/24
摘要： To mitigate kickback noise effect, the present invention provides a reference voltage generator for an analog-to-digital converter circuit. The reference voltage generator includes a bias generator, a bias converter and an output unit. The bias generator is used for generating a first bias voltage in accordance with a reference voltage. The bias converter is coupled to the bias generator and is used for converting the first bias voltage to a second bias voltage. The output unit is coupled to the bias converter and used for generating a first voltage to a load circuit in accordance with the second bias voltage.
摘要翻译：为了减轻反冲噪声效应，本发明提供了一种用于模数转换器电路的参考电压发生器。参考电压发生器包括偏置发生器，偏置转换器和输出单元。偏置发生器用于根据参考电压产生第一偏置电压。偏置转换器耦合到偏置发生器，并用于将第一偏置电压转换为第二偏置电压。输出单元耦合到偏置转换器，用于根据第二偏置电压向负载电路产生第一电压。

5. 发明授权

US07312740B2 Current steering digital-to-analog converter 有权
标题翻译：电流转向数模转换器
公开(公告)号：US07312740B2
公开(公告)日：2007-12-25
申请号：US11306256
申请日：2005-12-21
申请人： Kuo-Yu Chou
发明人： Kuo-Yu Chou
IPC分类号： H03M1/66
CPC分类号： H03M1/68 , H03M1/742
摘要： A current steering digital-to-analog converter (DAC) is provided. At least two lower-resolution DACs are used for converting a high-resolution digital signal. One of the two lower-resolution DACs is used for converting the most significant bits (MSB) of the high-resolution digital signal. The other of the two lower-resolution DACs is used for converting the least significant bits (LSB) of the high-resolution digital signal. By such arrangement, a device mismatch problem is avoided and the chance of variation occurrence during manufacturing process is reduced. The arrangement also simplifies the layout in the significantly scaled-down chip area.
摘要翻译：提供了一种电流转向数模转换器（DAC）。至少两个较低分辨率的DAC用于转换高分辨率数字信号。两个较低分辨率DAC中的一个用于转换高分辨率数字信号的最高有效位（MSB）。两个较低分辨率DAC中的另一个用于转换高分辨率数字信号的最低有效位（LSB）。通过这样的布置，避免了器件失配问题，减少了制造过程中发生变化的可能性。该布置还简化了显着缩小芯片面积的布局。

6. 发明授权

US07280336B2 Transient voltage detecting circuit 失效
标题翻译：瞬态电压检测电路
公开(公告)号：US07280336B2
公开(公告)日：2007-10-09
申请号：US10920309
申请日：2004-08-18
申请人： Kuo-Yu Chou
发明人： Kuo-Yu Chou
IPC分类号： H02H3/22
CPC分类号： H02H9/04
摘要： The invention provides a transient voltage detecting circuit for detecting a transient voltage occurring at a power supply or a ground of an electronic system. The circuit according to the invention includes a plurality of detecting units of which the outputs are initially latched by at least one voltage source. The circuit also includes a detecting device outputting a first logic according to the initial outputs of all of the detecting units. When the transient voltage occurs, it is ensured that the logic of the output of one of the detecting units is changed by the transient voltage or the decayed transient voltage, such that the decision device renewably outputs a second logic to trigger a resetting device of the electronic system in accordance with the outputs of all of the detecting units.
摘要翻译：本发明提供了一种瞬态电压检测电路，用于检测在电子系统的电源或接地处产生的瞬态电压。根据本发明的电路包括多个检测单元，其中输出端最初由至少一个电压源锁存。电路还包括根据所有检测单元的初始输出输出第一逻辑的检测装置。当发生瞬态电压时，确保其中一个检测单元的输出的逻辑由瞬态电压或衰减的瞬态电压改变，使得判定装置可再生地输出第二逻辑以触发复位装置电子系统根据所有检测单元的输出。

7. 发明申请

US20070090981A1 CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：电流转向数字到模拟转换器
公开(公告)号：US20070090981A1
公开(公告)日：2007-04-26
申请号：US11306256
申请日：2005-12-21
申请人： Kuo-Yu Chou
发明人： Kuo-Yu Chou
IPC分类号： H03M1/66
CPC分类号： H03M1/68 , H03M1/742
摘要： A current steering digital-to-analog converter (DAC) is provided. At least two lower-resolution DACs are used for converting a high-resolution digital signal. One of the two lower-resolution DACs is used for converting the most significant bits (MSB) of the high-resolution digital signal. The other of the two lower-resolution DACs is used for converting the least significant bits (LSB) of the high-resolution digital signal. By such arrangement, a device mismatch problem is avoided and the chance of variation occurrence during manufacturing process is reduced. The arrangement also simplifies the layout in the significantly scaled-down chip area.
摘要翻译：提供了一种电流转向数模转换器（DAC）。至少两个较低分辨率的DAC用于转换高分辨率数字信号。两个较低分辨率DAC中的一个用于转换高分辨率数字信号的最高有效位（MSB）。两个较低分辨率DAC中的另一个用于转换高分辨率数字信号的最低有效位（LSB）。通过这样的布置，避免了器件失配问题，减少了制造过程中发生变化的可能性。该布置还简化了显着缩小芯片面积的布局。

8. 发明申请

US20060087570A1 IMAGE SENSING DEVICE WITH PIXEL CORRECTION FUNCTION AND METHOD FOR CORRECTING PIXEL SENSING DATA IN IMAGE SENSING DEVICE 审中-公开
标题翻译：具有像素校正功能的图像感测装置和用于校正图像感测装置中的像素感测数据的方法
公开(公告)号：US20060087570A1
公开(公告)日：2006-04-27
申请号：US10905969
申请日：2005-01-28
申请人： Kuo-Yu Chou , Chih-Hua Tsai
发明人： Kuo-Yu Chou , Chih-Hua Tsai
IPC分类号： H04N9/64
CPC分类号： H04N5/367 , H04N1/401
摘要： An image sensing device includes a pixel sensing data processing unit, for receiving a pixel line sensing data to output first and second outputs. A controller receives the first output from the pixel sensing data processing unit, checks whether the pixel line sensing data include at least one defective pixel. If it has defective pixel, a correction rule is applied to compare the status data with a previously defective pixel. The correction rule includes comparing a state data of the previous defect pixels. If the defective pixel belongs to a regular pattern, the defective pixel is not corrected. A correction unit receives the second output and receives the correction status from the controller, and to correct the pixel and exports a display data. A recording unit records the status data of the defective pixel detected by the controller for comparing the status data of the next pixel line sensing data.
摘要翻译：图像感测装置包括像素感测数据处理单元，用于接收像素线感测数据以输出第一和第二输出。控制器从像素感测数据处理单元接收第一输出，检查像素线感测数据是否包括至少一个缺陷像素。如果它具有缺陷像素，则应用校正规则来将状态数据与先前缺陷的像素进行比较。校正规则包括比较先前缺陷像素的状态数据。如果缺陷像素属于规则图案，则不校正缺陷像素。校正单元接收第二输出并从控制器接收校正状态，并校正像素并输出显示数据。记录单元记录用于比较下一个像素行感测数据的状态数据的控制器检测到的缺陷像素的状态数据。

9. 发明授权

US08830361B2 Method of reducing column fixed pattern noise 有权
标题翻译：减少列固定图案噪声的方法
公开(公告)号：US08830361B2
公开(公告)日：2014-09-09
申请号：US13445350
申请日：2012-04-12
申请人： Po-Sheng Chou , Calvin Yi-Ping Chao , Kuo-Yu Chou , Honyih Tu , Yi-Che Chen
发明人： Po-Sheng Chou , Calvin Yi-Ping Chao , Kuo-Yu Chou , Honyih Tu , Yi-Che Chen
IPC分类号： H04N5/217 , H04N3/14 , H04N5/335 , H03M1/00
CPC分类号： H04N5/378 , G01J1/46 , H04N5/3658 , H04N5/37457 , H04N17/002
摘要： A method of reducing column fixed pattern noise including calibrating a readout circuit, wherein the readout circuit is electrically connected to at least one programmable gain amplifier and an analog-to-digital converter. Calibrating the readout circuit includes electrically disconnecting the readout circuit from a pixel output and electrically connecting a pixel reset input of the readout circuit to a pixel output signal input of the readout circuit. Calibrating the readout circuit further includes comparing a measured output of the readout circuit to a predetermined value and storing the comparison result in a non-transitory computer readable medium. The method further includes operating the readout circuit, the operating the readout circuit includes receiving a pixel sample signal and outputting a calibrated output based on an operating output and the stored comparison result.
摘要翻译：一种降低列固定模式噪声的方法，包括校准读出电路，其中读出电路电连接至至少一个可编程增益放大器和模 - 数转换器。校准读出电路包括将读出电路与像素输出电断开并将读出电路的像素复位输入电连接到读出电路的像素输出信号输入端。校准读出电路还包括将读出电路的测量输出与预定值进行比较，并将比较结果存储在非暂时的计算机可读介质中。所述方法还包括操作所述读出电路，所述读出电路的操作包括接收像素采样信号并基于操作输出和所存储的比较结果输出校准输出。

10. 发明授权

US08599292B2 CMOS sensor with low partition noise and low disturbance between adjacent row control signals in a pixel array 有权
公开(公告)号：US08599292B2
公开(公告)日：2013-12-03
申请号：US12858514
申请日：2010-08-18
申请人： Kuo-Yu Chou , Calvin Yi-Ping Chao
发明人： Kuo-Yu Chou , Calvin Yi-Ping Chao
IPC分类号： H04N5/335 , H01L27/00 , H01L31/062
CPC分类号： H01L27/14643 , H04N5/3577 , H04N5/374 , H04N5/376
摘要： A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state.

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