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1. 发明授权

US6148398A Setting/driving circuit for use with an integrated circuit logic unit having multi-function pins 有权
标题翻译：用于具有多功能引脚的集成电路逻辑单元的设置/驱动电路
公开(公告)号：US6148398A
公开(公告)日：2000-11-14
申请号：US286230
申请日：1999-04-05
申请人： Wen-Ching Chang , Lin-Hung Chang , Nai-Shung Chang
发明人： Wen-Ching Chang , Lin-Hung Chang , Nai-Shung Chang
IPC分类号： G06F1/22 , G06F9/00
CPC分类号： G06F1/22
摘要： A setting/driving circuit is provided for use in conjunction with an IC logic unit, such as a CPU having one or more multi-function pins, to provide two or more sets of data, such as a set of parameter data and a set of control data, via the same multi-function pins to the CPU. The setting/driving circuit includes a tri-state buffer and a parameter setting unit composed of two resistors and a switch, such as a jumper. When the tri-state buffer is disabled, the parameter data set by the switch is transferred to the multi-function pin of the CPU. On the other hand, when the tri-state buffer is enabled, the input data to the input port of the tri-state buffer is transferred to the multi-function pin of the CPU. The tri-state buffer can be integrated within the chip set without having to increase the total number of pins on the chip set so that the layout complexity on the motherboard can be simpler and thus easier to assemble compared to the prior art. Therefore, the proposed setting/driving circuit is easier and more cost-effective to implement on a computer motherboard than the prior art.
摘要翻译：提供了一种设置/驱动电路，用于与诸如具有一个或多个多功能引脚的CPU的IC逻辑单元一起使用，以提供两组或更多组数据，例如一组参数数据和一组控制数据，通过相同的多功能引脚到CPU。设置/驱动电路包括三态缓冲器和由两个电阻器组成的参数设置单元和诸如跳线的开关。当三态缓冲器被禁用时，由开关设置的参数数据被传送到CPU的多功能引脚。另一方面，当启用三态缓冲器时，三态缓冲器的输入端口的输入数据被传送到CPU的多功能引脚。三态缓冲器可以集成在芯片组中，而不必增加芯片组上的引脚总数，使得与现有技术相比，主板上的布局复杂度可以更简单并且因此更容易组装。因此，在现有技术中，所提出的设置/驱动电路在计算机主板上的实现更容易，更具成本效益。

2. 发明申请

US20210041072A1 Light Collector 有权
公开(公告)号：US20210041072A1
公开(公告)日：2021-02-11
申请号：US16614528
申请日：2018-04-27
申请人： Lin-Hung CHANG
发明人： Ching-Chieh Yang
IPC分类号： F21S11/00 , G02B3/08
摘要： A light collector (1), a plurality of densely distributed light collecting protrusions (11) protruding upward from the light collector (1), and a light collecting curved surface (111) is provided on the light collecting protrusions (11) in a curved manner; a plurality of densely distributed Fresnel lenses (12) protruding downward from the light collector (1), and a light emitting curved surface (121) being provided underneath the Fresnel lenses (12) in a curved manner. The light collector (1) of the present invention has low production cost and an effect of increasing light usage rate.

3. 发明授权

US3893152A Metal nitride oxide semiconductor integrated circuit structure 失效
标题翻译：金属氮化物半导体集成电路结构
公开(公告)号：US3893152A
公开(公告)日：1975-07-01
申请号：US38235573
申请日：1973-07-25
申请人： LIN HUNG CHANG
发明人： LIN HUNG CHANG
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L11/00 , H01L15/00
CPC分类号： H01L27/11517 , G11C16/0466 , H01L27/115 , Y10S148/085
摘要： Method and apparatus for providing a metal nitride oxide semiconductor (MNOS) memory in the form of a matrix array of either capacitors and/or transistors having polarizing potentials applied thereto for representing one of two binary logic states. Structurally, the array is comprised of a thin epitaxial layer of one type, for example n-type semiconductivity grown on a substrate of opposite or p-type semiconductivity. Parallel rows of silicon dioxide are infused into the epitaxial layer to provide strip regions of isolation between separated regions of first conductivity also forming substantially parallel rows. Transversely to the parallel sublayer rows of n-type semiconductivity and silicon dioxide isolation are a plurality of parallel columns of common gates, either metal or silicon. The columns of gates are separated from the parallel rows of n-type semiconductivity by intermediate contiguous layers of silicon dioxide and silicon nitride. Such a configuration describes a matrix array of capacitors; however, a matrix of transistors is formed by additionally diffusing a dopant of for example p+type semiconductivity into the regions of n-type semiconductivity on either side of the parallel columns of common gates.
摘要翻译：用于提供金属氮化物半导体（MNOS）存储器的形式的金属氮化物半导体（MNOS）存储器，其形式为具有施加到其上的用于表示两个二进制逻辑状态之一的具有极化电位的电容器和/或晶体管的矩阵阵列。在结构上，该阵列由一种类型的薄外延层组成，例如在相对或p型半导体性的衬底上生长的n型半导电性。平行的二氧化硅排被输入到外延层中以提供在形成基本平行的行的分离的第一导电区域之间的隔离带。与n型半导体性和二氧化硅隔离的平行子层行相反地是多个平行的公共栅极列，金属或硅。栅极的列通过二氧化硅和氮化硅的中间连续层与n型半导体性的平行排分离。这种配置描述了电容器的矩阵阵列; 然而，晶体管的矩阵通过将例如p +型半导体性的掺杂剂额外扩散到公共栅极的平行列的任一侧上的n型半导体性区域中而形成。

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