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1. 发明授权

US08621408B2 Progressive circuit evaluation for circuit optimization 有权
标题翻译：电路优化的进步电路评估
公开(公告)号：US08621408B2
公开(公告)日：2013-12-31
申请号：US13438602
申请日：2012-04-03
申请人： Mahesh A. Iyer , Robert Walker , Sudipto Kundu
发明人： Mahesh A. Iyer , Robert Walker , Sudipto Kundu
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.
摘要翻译：描述了用于优化电路设计的系统和技术。一些实施例减少库中的门数（例如，通过动态修剪库），这被考虑用于优化。一些实施例创建线性延迟模型，并且使用线性延迟模型而不是非线性延迟模型来基本上减少检查特定替换门是否改善电路设计的一个或多个度量所需的计算量。一些实施例确定用于处理库中的门或用于处理门的输入引脚的顺序，以便于早期拒绝门库中的候选门。在一些实施例中，候选门转换的影响的评估逐渐地逐级地逐级地进行，直到门转换降级一个或多个度量为止。

2. 发明申请

US20130145336A1 PROGRESSIVE CIRCUIT EVALUATION FOR CIRCUIT OPTIMIZATION 有权
标题翻译：电路优化的渐进式电路评估
公开(公告)号：US20130145336A1
公开(公告)日：2013-06-06
申请号：US13438602
申请日：2012-04-03
申请人： Mahesh A. Iyer , Robert Walker , Sudipto Kundu
发明人： Mahesh A. Iyer , Robert Walker , Sudipto Kundu
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.
摘要翻译：描述了用于优化电路设计的系统和技术。一些实施例减少库中的门数（例如，通过动态修剪库），这被考虑用于优化。一些实施例创建线性延迟模型，并且使用线性延迟模型而不是非线性延迟模型来基本上减少检查特定替换门是否改善电路设计的一个或多个度量所需的计算量。一些实施例确定用于处理库中的门或用于处理门的输入引脚的顺序，以便于早期拒绝门库中的候选门。在一些实施例中，候选门转换的影响的评估逐渐地逐级地逐级地进行，直到门转换降级一个或多个度量为止。

3. 发明授权

US08418116B2 Zone-based optimization framework for performing timing and design rule optimization 有权
标题翻译：基于区域的优化框架，用于执行定时和设计规则优化
公开(公告)号：US08418116B2
公开(公告)日：2013-04-09
申请号：US12697168
申请日：2010-01-29
申请人： Robert Walker , Mahesh A. Iyer , Amir H. Mottaez
发明人： Robert Walker , Mahesh A. Iyer , Amir H. Mottaez
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F17/5081
摘要： Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation.
摘要翻译：本发明的一些实施例提供用于有效地优化一个或多个多模式多角（MCMM）场景的电路设计的技术和系统。系统可以选择用于逻辑门的优化变换，其如果应用于逻辑门，则不降低逻辑门的本地上下文中的定时度量。接下来，系统可以确定将优化变换应用于逻辑门是否会降低逻辑门周围区域中的定时度量。如果是这样，系统可以拒绝优化转换。否则，系统可以确定将优化变换应用于逻辑门是否会降低电路设计中的定时度量。如果是这样，系统可以拒绝优化转换。否则，系统可以接受优化转换。

4. 发明授权

US08239800B2 Method and apparatus for determining a robustness metric for a circuit design 有权
标题翻译：用于确定电路设计的鲁棒性度量的方法和装置
公开(公告)号：US08239800B2
公开(公告)日：2012-08-07
申请号：US12697088
申请日：2010-01-29
申请人： Mahesh A. Iyer , Amir H. Mottaez
发明人： Mahesh A. Iyer , Amir H. Mottaez
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/50
摘要： Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and base slacks for the endpoints in a base implementation of the circuit design. The system can then determine the new critical path delays and new slacks for the endpoints in a new implementation of the circuit design. Next, the system determines slack differences for the endpoints using the new slacks and the base slacks. Finally, for each endpoint, the system can determine an endpoint change indicator using the associated slack difference, the base critical path delay, and the new critical path delay. A pathgroup change indicator can be determined using endpoint change indicators. A design change indicator can be determined using pathgroup change indicators or scenario change indicators. A design flow change indicator can be determined using design change indicators.
摘要翻译：一些实施例提供用于确定端点，路径组，设计和/或流的改变指示符的技术和系统。该系统可以在电路设计的基本实现中确定端点的基本关键路径延迟和基础间隙。然后，系统可以在电路设计的新实现中确定端点的新的关键路径延迟和新的松弛。接下来，系统使用新的松弛和基座松弛来确定端点的松弛差异。最后，对于每个端点，系统可以使用相关的松弛差，基本关键路径延迟和新的关键路径延迟来确定端点变化指示符。可以使用端点更改指示器来确定路径组更改指示符。可以使用路径组变更指标或情景变化指标来确定设计变更指标。可以使用设计变更指标来确定设计流量变化指标。

5. 发明申请

US20120030642A1 HYPER-CONCURRENT MULTI-SCENARIO OPTIMIZATION 有权
标题翻译：超多场多场景优化
公开(公告)号：US20120030642A1
公开(公告)日：2012-02-02
申请号：US12845545
申请日：2010-07-28
申请人： Amir H. Mottaez , Mahesh A. Iyer
发明人： Amir H. Mottaez , Mahesh A. Iyer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , G06F2217/08 , G06F2217/84
摘要： Some embodiments of the present invention provide techniques and systems for performing aggressive and dynamic scenario reduction during different phases of optimization, e.g., during delay, area, leakage and DRC (design rule check) optimization. Specifically, essential scenarios at gates and timing end-points can be identified and then used during the dynamic scenario reduction process. In some embodiments, margin values associated with various constraints can be used to determine the set of essential scenarios to account for constrained objects that are near critical in addition to the constrained objects that are the worst violators. In some embodiments, at any point during the optimization process, only the set of essential scenarios are kept active, thereby substantially reducing runtime and memory requirements without compromising on the quality of results.
摘要翻译：本发明的一些实施例提供了用于在优化的不同阶段（例如在延迟，区域，泄漏和DRC（设计规则检查）优化期间）执行积极和动态场景减少的技术和系统。具体来说，可以识别门和定时终点的基本情景，然后在动态场景减少过程中使用。在一些实施例中，与各种约束相关联的边界值可用于确定除了受限制的对象之外的接近关键的约束对象的基本场景的集合，这些约束对象是最严重的违规者。在一些实施例中，在优化过程中的任何时刻，只有一组基本场景保持活动，从而大大减少运行时和存储器的需求，而不会影响结果的质量。

6. 发明申请

US20110289464A1 GLOBAL TIMING MODELING WITHIN A LOCAL CONTEXT 有权
标题翻译：在本地语境下的全局时序建模
公开(公告)号：US20110289464A1
公开(公告)日：2011-11-24
申请号：US12783915
申请日：2010-05-20
申请人： Mahesh A. Iyer , Amir H. Mottaez , Rajnish K. Prasad
发明人： Mahesh A. Iyer , Amir H. Mottaez , Rajnish K. Prasad
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045 , G06F17/505 , G06F2217/08 , G06F2217/84
摘要： Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate.
摘要翻译：本发明的一些实施例提供了用于确定和使用边缘值的技术和系统。可以确定逻辑门的输出引脚的到达时间。接下来，可以确定逻辑门的输出引脚所需的时间。每个所需的时间可以与路径组中的定时终点相关联，受该引脚的影响。然后，系统可以通过计算所需时间和到达时间之间的差异来确定逻辑门的输出引脚处的第一组松弛值。接下来，系统可以通过计算在路径组中的定时终点处的第一组松弛值和第二组松弛值之间的差来确定逻辑门的输出引脚处的一组余量值。接下来，系统可以使用一组余量值来优化逻辑门。

7. 发明授权

US5559811A Method for identifying untestable and redundant faults in sequential logic circuits. 失效
标题翻译：在顺序逻辑电路中识别不可测和冗余故障的方法。
公开(公告)号：US5559811A
公开(公告)日：1996-09-24
申请号：US599289
申请日：1996-02-09
申请人： Miron Abramovici , Mahesh A. Iyer
发明人： Miron Abramovici , Mahesh A. Iyer
IPC分类号： G01R31/3183 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318586 , G01R31/318342 , G01R31/318371
摘要： A method of identifying redundant and untestable faults in a sequential logic circuit. A lead in the circuit is selected and the circuit is analyzed to determine which faults would be hypothetically undetectable at a given time frame if the selected circuit lead were unable to assume a logic 0 at a starting time frame, and which faults would be hypothetically undetectable at the given time frame if the selected circuit lead were unable to assume a logic 1 at the starting time frame. Faults that would be undetectable at the given time frame in both hypothetical cases are identified as redundant and untestable faults. This analysis may be repeated for each of a plurality of time frames in a range of time frames which includes the starting time frame. Faults whose detection would not be possible if the selected lead were unable to assume a given value at the starting time frame may be determined based on a sequential implication procedure comprising the propagation of uncontrollability indicators and the backward propagation of unobservability indicators. An uncontrollability indicator for the given (0 or 1) value is assigned to the selected circuit lead and is propagated through the circuit and/or through a range of time frames according to a predetermined set of propagation rules. Unobservability indicators are generated in the circuit at various time frames based on the uncontrollability indicators, and these unobservability indicators are then propagated backward through the circuit and/or backward through the range of time frames, also in accordance with a predetermined set of propagation rules. The hypothetically undetectable faults are then determined based on the resultant indicators and their corresponding circuit leads and associated time frames.
摘要翻译：一种在顺序逻辑电路中识别冗余和不可测故障的方法。选择电路中的引线，并分析电路，以确定在给定时间帧，如果所选择的电路引线在起始时间段内不能采用逻辑0，哪些故障在假设上是不可检测的，哪些故障将被假设为不可检测的如果所选择的电路引线在起始时间段内不能采用逻辑1，则在给定的时间帧。在两种假设情况下，在给定时间框架内将无法检测到的故障被认为是冗余和不可测试的故障。可以在包括起始时间帧的时间范围内的多个时间帧中的每一个重复该分析。可以根据包括不可控性指标的传播和不可观察性指示器的反向传播的顺序暗示过程来确定如果所选择的引线在起始时间帧不能采用给定值，则检测不可能的故障。给定（0或1）值的不可控性指示符被分配给所选择的电路引线，并且根据预定的一组传播规则通过电路和/或通过一段时间帧传播。基于不可控性指示器，在不同时间帧在电路中产生不可观察性指示符，并且这些不可观察性指示符随后也通过电路向后传播和/或在后面的时间范围内，也根据预定的一组传播规则。然后基于所得到的指示符及其对应的电路引线和相关时间帧来确定假设不可检测的故障。

8. 发明申请

US20220116041A1 Power Management using Voltage Islands on Programmable Logic Devices 有权
公开(公告)号：US20220116041A1
公开(公告)日：2022-04-14
申请号：US17559287
申请日：2021-12-22
申请人： Mahesh K. Kumashikar , Ankireddy Nalamalpu , MD Altaf Hossain , Dheeraj Subbareddy , Atul Maheshwari , Yuet Li , Mahesh A. Iyer
发明人： Mahesh K. Kumashikar , Ankireddy Nalamalpu , MD Altaf Hossain , Dheeraj Subbareddy , Atul Maheshwari , Yuet Li , Mahesh A. Iyer
IPC分类号： H03K19/177
摘要： Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.

9. 发明授权

US08949764B2 Excluding library cells for delay optimization in numerical synthesis 有权
标题翻译：排除库单元进行数值合成中的延迟优化
公开(公告)号：US08949764B2
公开(公告)日：2015-02-03
申请号：US13479807
申请日：2012-05-24
申请人： Mahesh A. Iyer , Amir H. Mottaez
发明人： Mahesh A. Iyer , Amir H. Mottaez
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively.
摘要翻译：描述排除库单元的方法和系统。一些实施例为库单元类型的定时弧接收通用逻辑努力值和可选的通用寄生延迟值。接下来，排除库单元类型的库单元，其定时弧的特定逻辑努力值大于通用逻辑努力值大于第一阈值和/或可选地其定时弧的特定寄生延迟值大于通用寄生延迟值大于第二阈值。可以基于至少一些剩余的库单元来确定新的通用逻辑努力值和可选的新的通用寄生延迟值。可以迭代地执行排除库单元和确定新的通用逻辑努力值以及可选的新的通用寄生延迟值的过程。

10. 发明申请

US20140007037A1 ESTIMATING OPTIMAL GATE SIZES BY USING NUMERICAL DELAY MODELS 有权
标题翻译：通过使用数字延迟模型估计最优门尺寸
公开(公告)号：US20140007037A1
公开(公告)日：2014-01-02
申请号：US13537880
申请日：2012-06-29
申请人： Amir H. Mottaez , Mahesh A. Iyer
发明人： Amir H. Mottaez , Mahesh A. Iyer
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068
摘要： Systems and techniques are described for estimating optimal gate sizes in a circuit design using numerical delay models of cells and cell types in a technology library. Gate sizes are optimized in the circuit design in a reverse-levelized processing order. Gates that are at the same level in the reverse-levelized processing order, and whose inputs are electrically connected to the same driver output are optimized together. A closed-form expression is used to determine the optimized size for each gate in a set of gates that are optimized together. Some embodiments perform multiple optimization iterations, wherein in each optimization iteration all of the gates in the circuit design are processed in the reverse-levelized processing order. The iterative optimization process terminates when one or more termination conditions are met.
摘要翻译：描述了使用技术库中的单元和单元类型的数值延迟模型来估计电路设计中的最佳栅极尺寸的系统和技术。栅极尺寸在电路设计中以反向级别化处理顺序进行了优化。处于相反级别的处理顺序处于相同级别的门并且其输入电连接到相同的驱动器输出的门优化在一起。闭合表达式用于确定一组优化的一组门中每个门的优化大小。一些实施例执行多个优化迭代，其中在每个优化迭代中，电路设计中的所有门都以反向均衡的处理顺序被处理。当满足一个或多个终止条件时，迭代优化过程终止。

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