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1. 发明申请

US20080248641A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080248641A1
公开(公告)日：2008-10-09
申请号：US11905074
申请日：2007-09-27
申请人： Mariko Makabe
发明人： Mariko Makabe
IPC分类号： H01L21/3205
CPC分类号： H01L21/823462
摘要： A method of manufacturing a semiconductor device according to this invention includes; forming a first region in which a first insulating film is formed on a semiconductor substrate surface and a second region on which the semiconductor substrate surface is exposed; cleaning the semiconductor substrate surface exposed in the second region with a cleaning fluid; removing a chemical oxide film formed on the semiconductor substrate surface in the second region with the cleaning fluid; forming a second insulating film having a film thickness different from that of the first insulating film on the semiconductor substrate surface in the second region; and forming a gate electrode film on the first insulating film and the second insulating film to form a pattern in the gate electrode film (and the first insulating film and the second insulating film formed under the gate electrode film). In removing the oxide film, the oxide film is removed by processing the semiconductor substrate in the presence of a hydrogen gas at a temperature of not less than 940° and not more than 990° and a pressure of not less than 30 Torr and not more than 150 Torr.
摘要翻译：根据本发明的制造半导体器件的方法包括：形成在半导体衬底表面上形成第一绝缘膜的第一区域和暴露所述半导体衬底表面的第二区域; 用清洗液清洗在第二区域中暴露的半导体衬底表面; 用所述清洁流体除去在所述第二区域中形成在所述半导体衬底表面上的化学氧化物膜; 在所述第二区域中形成在所述半导体衬底表面上具有不同于所述第一绝缘膜的膜厚度的第二绝缘膜; 以及在所述第一绝缘膜和所述第二绝缘膜上形成栅电极膜，以在所述栅电极膜（以及形成在所述栅电极膜下方的所述第一绝缘膜和所述第二绝缘膜）之间形成图案。在除去氧化物膜时，通过在不低于940℃且不大于990°的温度和不低于30托的压力下在氢气存在下处理半导体衬底来除去氧化物膜，而不是更多超过150乇。

2. 发明授权

US06614081B2 High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions 失效
标题翻译：具有具有氮化物中心部分和氧化物端部部分的栅极绝缘膜的LDD结构的高性能MOS晶体管
公开(公告)号：US06614081B2
公开(公告)日：2003-09-02
申请号：US09824672
申请日：2001-04-04
申请人： Mariko Makabe , Shin Koyama , Koichi Ando
发明人： Mariko Makabe , Shin Koyama , Koichi Ando
IPC分类号： H01L2976
CPC分类号： H01L21/28202 , H01L29/512 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A Metal Oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end portion located on each side of the central portion, the end portion being thicker than the central portion and formed of an oxide insulating film. The MOS transistor also includes a p-type gate electrode formed on the gate insulating film, sidewalls formed on both sides of the gate insulating film and the gate electrode, a pair of p-type source/drain areas formed in surface portions of the silicon substrate, and a channel area located between the pair of source/drain areas.
摘要翻译：金属氧化物半导体（MOS）晶体管包括设置在硅衬底的表面上的栅极绝缘膜。栅极绝缘膜具有形成在硅衬底上并包括氮化物绝缘膜的中心部分和位于中心部分的每一侧上的端部，其端部比中心部分厚，并由氧化物绝缘膜形成。 MOS晶体管还包括形成在栅极绝缘膜上的p型栅极电极，形成在栅极绝缘膜和栅电极两侧的侧壁，形成在硅的表面部分中的一对p型源极/漏极区域衬底和位于一对源/漏区之间的沟道区。

3. 发明授权

US07776686B2 Method of fabricating a non-volatile memory element including nitriding and oxidation of an insulating film 失效
标题翻译：制造包括绝缘膜的氮化和氧化的非易失性存储元件的方法
公开(公告)号：US07776686B2
公开(公告)日：2010-08-17
申请号：US11368635
申请日：2006-03-07
申请人： Mariko Makabe , Eiji Hasegawa
发明人： Mariko Makabe , Eiji Hasegawa
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/02249 , H01L21/3145 , H01L27/115 , H01L27/11521 , H01L29/7885
摘要： An interpoly insulating film is modified in the film quality, while preventing generation of trap sites. A floating gate 101 is provided on a channel-forming region in the vicinity of the surface of a silicon substrate 112, an interpoly insulating film 134 is provided so as to contact with the floating gate 101, and a control gate 103 is provided so as to contact with the interpoly insulating film 134 and so as to be opposed to at least a part of the floating gate 101. A process step of providing the interpoly insulating film 134 further includes a step of forming on the floating gate 101, the interpoly insulating film 134 so as to contact with the floating gate 101, and a step of exposing, subsequently to the formation of the interpoly insulating film 134, the interpoly insulating film 134 to an atmosphere containing a nitrogen-containing gas and oxygen, to thereby simultaneously proceed nitriding and oxidation of the interpoly insulating film 134.
摘要翻译：在膜的质量上改变了多层绝缘膜，同时防止产生陷阱位置。在硅基板112的表面附近的沟道形成区域上设置浮置栅极101，设置与浮置栅极101接触的多晶硅绝缘膜134，并且设置控制栅极103 与多晶硅绝缘膜134接触并且与浮栅101的至少一部分相对。提供多晶硅绝缘膜134的工艺步骤还包括在浮栅101上形成多余绝缘的步骤膜134，以便与浮置栅极101接触，以及随后将多晶硅绝缘膜134形成为多余绝缘膜134而暴露于含有含氮气体和氧气的气氛中的步骤，从而同时进行间隔绝缘膜134的氮化和氧化。

4. 发明申请

US20060205155A1 Method of fabricating a non-volatile memory element 失效
标题翻译：制造非易失性存储元件的方法
公开(公告)号：US20060205155A1
公开(公告)日：2006-09-14
申请号：US11368635
申请日：2006-03-07
申请人： Mariko Makabe , Eiji Hasegawa
发明人： Mariko Makabe , Eiji Hasegawa
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/02249 , H01L21/3145 , H01L27/115 , H01L27/11521 , H01L29/7885
摘要： An interpoly insulating film is modified in the film quality, while preventing generation of trap sites. A floating gate 101 is provided on a channel-forming region in the vicinity of the surface of a silicon substrate 112, an interpoly insulating film 134 is provided so as to contact with the floating gate 101, and a control gate 103 is provided so as to contact with the interpoly insulating film 134 and so as to be opposed to at least a part of the floating gate 101. A process step of providing the interpoly insulating film 134 further includes a step of forming on the floating gate 101, the interpoly insulating film 134 so as to contact with the floating gate 101, and a step of exposing, subsequently to the formation of the interpoly insulating film 134, the interpoly insulating film 134 to an atmosphere containing a nitrogen-containing gas and oxygen, to thereby simultaneously proceed nitriding and oxidation of the interpoly insulating film 134.
摘要翻译：在膜的质量上改变了多层绝缘膜，同时防止产生陷阱位置。在硅基板112的表面附近的沟道形成区域上设置浮置栅极101，设置与浮置栅极101接触的多晶硅绝缘膜134，并且设置控制栅极103 与多晶硅绝缘膜134接触并且与浮栅101的至少一部分相对。提供多晶硅绝缘膜134的工艺步骤还包括在浮栅101上形成多余绝缘的步骤膜134，以便与浮置栅极101接触，以及随后将多晶硅绝缘膜134形成为多余绝缘膜134而暴露于含有含氮气体和氧气的气氛中，从而同时进行间隔绝缘膜134的氮化和氧化。

5. 发明授权

US06603179B2 Semiconductor apparatus including CMOS circuits and method for fabricating the same 有权
标题翻译：包括CMOS电路的半导体装置及其制造方法
公开(公告)号：US06603179B2
公开(公告)日：2003-08-05
申请号：US09995513
申请日：2001-11-28
申请人： Koichi Ando , Mariko Makabe , Shin Koyama
发明人： Koichi Ando , Mariko Makabe , Shin Koyama
IPC分类号： H01L31119
CPC分类号： H01L21/823857 , H01L27/0922

6. 发明授权

US06794258B2 High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions 失效
标题翻译：具有具有氮化物中心部分和氧化物端部的栅极绝缘膜的LDD结构的高性能MOS晶体管
公开(公告)号：US06794258B2
公开(公告)日：2004-09-21
申请号：US10606294
申请日：2003-06-26
申请人： Mariko Makabe , Shin Koyama , Koichi Ando
发明人： Mariko Makabe , Shin Koyama , Koichi Ando
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L29/512 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A metal oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end portion located on each side of the central portion, the end portion being thicker than the central portion and formed of an oxide insulating film. The MOS transistor also includes a p-type gate electrode formed on the gate insulating film, sidewalls formed on both sides of the gate insulating film and the gate electrode, a pair of p-type source/drain areas formed in surface portions of the silicon substrate, and a channel area located between the pair of source/drain areas.
摘要翻译：金属氧化物半导体（MOS）晶体管包括设置在硅衬底的表面上的栅极绝缘膜。栅极绝缘膜具有形成在硅衬底上并包括氮化物绝缘膜的中心部分和位于中心部分的每一侧上的端部，其端部比中心部分厚，并由氧化物绝缘膜形成。 MOS晶体管还包括形成在栅极绝缘膜上的p型栅极电极，形成在栅极绝缘膜和栅电极两侧的侧壁，形成在硅的表面部分中的一对p型源极/漏极区域衬底和位于一对源/漏区之间的沟道区。

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