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1. 发明授权

US08775988B2 Decentralized dynamically scheduled parallel static timing analysis 失效
标题翻译：分散式动态调度并行静态时序分析
公开(公告)号：US08775988B2
公开(公告)日：2014-07-08
申请号：US13150445
申请日：2011-06-01
申请人： Mark A. Lavin , David J. Hathaway , Kerim Kalafala , Jeffrey S. Piaget , Chandramouli Visweswariah
发明人： Mark A. Lavin , David J. Hathaway , Kerim Kalafala , Jeffrey S. Piaget , Chandramouli Visweswariah
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.
摘要翻译：一种用于执行并行静态时序分析的方法，其中多个进程独立地更新时序图，而不需要通过中央协调器模块进行通信。本地处理队列用于减少锁定开销，而不会导致过大的负载不平衡。对由多个互连节点形成的时序图表示的电路设计进行并行分析，该方法包括：使用计算机创建准备处理独立节点的共享工作队列; 将独立节点从工作队列分配到至少两个并行计算过程，同时执行其节点分析计算; 以及通过更新从所述节点分析获得的经处理的独立节点的值来修改所述电路设计，所述至少两个并行计算处理独立地更新所述共享工作队列以处理新的多个独立节点。

2. 发明授权

US08423947B2 Gridded glyph geometric objects (L3GO) design method 失效
标题翻译：格栅字形几何对象（L3GO）的设计方法
公开(公告)号：US08423947B2
公开(公告)日：2013-04-16
申请号：US12047566
申请日：2008-03-13
申请人： Mark A. Lavin , Thomas Ludwig , Gregory A. Northrop , Robert T. Sayah
发明人： Mark A. Lavin , Thomas Ludwig , Gregory A. Northrop , Robert T. Sayah
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs.
摘要翻译：一种格栅字形几何对象（L3GO）集成电路（IC）设计的方法，其中L3GO电路设计中的至少一个级间连接在L3GO网格上表示为点阵字形（PMG）。每个PMG在下一个相邻（上和下）层上连接一对导体，并包括一个包含在笼中的点字形的阵列（一维或二维）。点字形可以具有均匀的尺寸并且可以在最小间距上。每个PMG还可以包括在上下层的凸缘。默认法兰确保足够的覆盖由点字形表示的切割形状。

3. 发明申请

US20120311514A1 Decentralized Dynamically Scheduled Parallel Static Timing Analysis 失效
标题翻译：分散式动态调度并行静态时序分析
公开(公告)号：US20120311514A1
公开(公告)日：2012-12-06
申请号：US13150445
申请日：2011-06-01
申请人： Mark A. Lavin , David J. Hathaway , Kerim Kalafala , Jeffrey S. Piaget , Chandramouli Visweswariah
发明人： Mark A. Lavin , David J. Hathaway , Kerim Kalafala , Jeffrey S. Piaget , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.
摘要翻译：一种用于执行并行静态时序分析的方法，其中多个进程独立地更新时序图，而不需要通过中央协调器模块进行通信。本地处理队列用于减少锁定开销，而不会导致过大的负载不平衡。对由多个互连节点形成的时序图表示的电路设计进行并行分析，该方法包括：使用计算机创建准备处理独立节点的共享工作队列; 将独立节点从工作队列分配到至少两个并行计算过程，同时执行其节点分析计算; 以及通过更新从所述节点分析获得的经处理的独立节点的值来修改所述电路设计，所述至少两个并行计算处理独立地更新所述共享工作队列以处理新的多个独立节点。

4. 发明授权

US07840057B2 Simultaneous computation of multiple points on one or multiple cut lines 有权
标题翻译：在一条或多条切割线上同时计算多个点
公开(公告)号：US07840057B2
公开(公告)日：2010-11-23
申请号：US11874281
申请日：2007-10-18
申请人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
发明人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
IPC分类号： G06K9/00 , G06F17/50
CPC分类号： G03F1/36
摘要： Methods, and program storage devices, for performing model-based optical proximity correction by providing a region of interest (ROI) having an interaction distance and locating at least one polygon within the ROI. A cut line of sample points representative of a set of vertices, or plurality of cut lines, are generated within the ROI across at least one lateral edge of the polygon(s). An angular position, and first and second portions of the cut line residing on opposing sides of an intersection between the cut line and the lateral edge of the polygon are determined, followed by generating a new ROI by extending the original ROI beyond its interaction distance based on such angular position, and first and second portions of the cut line. In this manner, a variety of new ROIs may be generated, in a variety of different directions, to ultimately correct for optical proximity.
摘要翻译：方法和程序存储设备，用于通过提供具有交互距离的感兴趣区域（ROI）和定位ROI内的至少一个多边形来执行基于模型的光学邻近度校正。在多边形的至少一个侧边缘上，在ROI内产生代表一组顶点或多个切割线的采样点的切割线。确定角位置，并且切割线的位于切割线和多边形的侧边缘之间的交叉点的相对侧上的切割线的第一和第二部分，然后通过将原始ROI延伸超过其相互作用距离来生成新的ROI 在这种角度位置上，以及切割线的第一和第二部分。以这种方式，可以在各种不同的方向上产生各种新的ROI，以最终校正光学邻近度。

5. 发明申请

US20090235215A1 GRIDDED GLYPH GEOMETRIC OBJECTS (L3GO) DESIGN METHOD 失效
标题翻译： GRIDDED GLYPH几何对象（L3GO）设计方法
公开(公告)号：US20090235215A1
公开(公告)日：2009-09-17
申请号：US12047566
申请日：2008-03-13
申请人： Mark A. Lavin , Thomas Ludwig , Gregory A. Northrop , Robert T. Sayah
发明人： Mark A. Lavin , Thomas Ludwig , Gregory A. Northrop , Robert T. Sayah
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs.
摘要翻译：一种格栅字形几何对象（L3GO）集成电路（IC）设计的方法，其中L3GO电路设计中的至少一个级间连接在L3GO网格上表示为点阵字形（PMG）。每个PMG在下一个相邻（上和下）层上连接一对导体，并包括一个包含在笼中的点字形的阵列（一维或二维）。点字形可以具有均匀的尺寸并且可以在最小间距上。每个PMG还可以包括在上下层的凸缘。默认法兰确保足够的覆盖由点字形表示的切割形状。

6. 发明申请

US20080244503A1 System for Coloring a Partially Colored Design in an Alternating Phase Shift Mask 失效
标题翻译：用于在交替相移掩模中着色部分彩色设计的系统
公开(公告)号：US20080244503A1
公开(公告)日：2008-10-02
申请号：US12121371
申请日：2008-05-15
申请人： Ioana Graur , Young O. Kim , Mark A. Lavin , Lars W. Liebmann
发明人： Ioana Graur , Young O. Kim , Mark A. Lavin , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G03F1/30
摘要： A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e.g., be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout.
摘要翻译：一种设计用于投影集成电路设计的图像的交替相移掩模的方法。相位单元在分层电路设计的每个单元内，例如单元，阵列，网络或网络和/或单元阵列，可以是相位形状的二进制可着色。分层单元内的相位或颜色的分配将被正确地二进制着色以满足平版印刷，可制造性和其他设计规则，统称为着色规则。在与其他单元的组装期间，层级单元中的相位的着色可能改变（例如，被颠倒或翻转），但是保留了分层单元的正确的二值可着色性，这简化了集成电路布局的组装。

7. 发明申请

US20080232675A1 SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 失效
标题翻译：集成电路系统缺陷的搜索与分析系统
公开(公告)号：US20080232675A1
公开(公告)日：2008-09-25
申请号：US12132710
申请日：2008-06-04
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

8. 发明授权

US07404174B2 method for generating a set of test patterns for an optical proximity correction algorithm 有权
标题翻译：用于生成用于光学邻近校正算法的一组测试图案的方法
公开(公告)号：US07404174B2
公开(公告)日：2008-07-22
申请号：US10710648
申请日：2004-07-27
申请人： David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.
摘要翻译：一种合成布局图案以测试光学邻近校正算法的方法。该方法包括以下步骤：在一组沃尔什模式矩阵中体现沃尔什模式; 从所述一组沃尔什图案矩阵中处理矩阵组以形成一组测试矩阵; 将测试矩阵的集合映射到测试模式集合。

9. 发明授权

US07131104B2 Fast and accurate optical proximity correction engine for incorporating long range flare effects 有权
标题翻译：快速准确的光学邻近校正引擎，用于引入远射闪光效果
公开(公告)号：US07131104B2
公开(公告)日：2006-10-31
申请号：US10844794
申请日：2004-05-13
申请人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman , Zheng Chen , Maharaj Mukherjee
发明人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman , Zheng Chen , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70
摘要： A method is described for performing model-based optical proximity corrections on a mask layout used in an optical lithography process having a plurality of mask shapes. Model-based optical proximity correction is performed by computing the image intensity on selected evaluation points on the mask layout. The image intensity to be computed includes optical flare and stray light effects due to the interactions between the shapes on the mask layout. The computation of the image intensity involves sub-dividing the mask layout into a plurality of regions, each region at an increasing distance from the evaluation point. The contributions of the optical flare and stray light effects due to mask shapes in each of the regions are then determined. Finally, all the contributions thus obtained are combined to obtain the final computation of the image intensity at the selected point.
摘要翻译：描述了一种用于在具有多个掩模形状的光学光刻工艺中使用的掩模布局上执行基于模型的光学邻近校正的方法。基于模型的光学邻近校正通过在掩模布局上的所选评估点上计算图像强度来执行。要计算的图像强度由于掩模布局上的形状之间的相互作用而包括光学耀斑和杂散光效应。图像强度的计算涉及将掩模布局分成多个区域，每个区域距离评估点增加的距离。然后确定由于每个区域中的掩模形状引起的光学耀斑和杂散光效应的贡献。最后，将所得到的所有贡献结合起来，以获得所选点处图像强度的最终计算。

10. 发明授权

US07010776B2 Extending the range of lithographic simulation integrals 有权
标题翻译：扩展光刻模拟积分的范围
公开(公告)号：US07010776B2
公开(公告)日：2006-03-07
申请号：US10694466
申请日：2003-10-27
申请人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
发明人： Gregg M. Gallatin , Emanuel Gofman , Kafai Lai , Mark A. Lavin , Maharaj Mukherjee , Dov Ramm , Alan E. Rosenbluth , Shlomo Shlafman
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70
摘要： A method for calculating long-range image contributions from mask polygons. An algorithm is introduced having application to Optical Proximity Correction in optical lithography. A finite integral for each sector of a polygon replaces an infinite integral. Integrating over two triangles, rather than integrating on the full sector, achieves a finite integral. An analytical approach is presented for a power law kernel to reduce the numerical integration of a sector to an analytical expression evaluation. The mask polygon is divided into regions to calculate interaction effects, such as intermediate-range and long-range effects, by truncating the mask instead of truncating the kernel function.
摘要翻译：一种用于从掩模多边形计算长距离图像贡献的方法。引入了一种应用于光学光刻中的光学邻近校正的算法。多边形的每个扇区的有限积分代替无限积分。整合在两个三角形上，而不是整体上整合，实现了一个有限积分。针对幂律内核提出了一种分析方法，以减少一个部门与分析表达式评估的数值整合。掩模多边形被划分为区域，以通过截断掩码而不是截断内核函数来计算交互效应，例如中间范围和远程效果。

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