专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08756451B2 Frequency synthesis methods and systems 有权
标题翻译：频率合成方法和系统
公开(公告)号：US08756451B2
公开(公告)日：2014-06-17
申请号：US13251220
申请日：2011-10-01
申请人： Mark L. Neidengard , Nasser A. Kurd , Robert J. Greiner , Vaughn J. Grossnickle
发明人： Mark L. Neidengard , Nasser A. Kurd , Robert J. Greiner , Vaughn J. Grossnickle
IPC分类号： G06F1/00 , H03L7/06 , H03L7/00
CPC分类号： H03L7/23 , G06F1/08 , H03L7/183
摘要： Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.
摘要翻译：综合参考频率的多层方法和系统，并根据多个优先级标准控制一层或多层。频率合成器的第一层可以包括第一锁相环（PLL），其可以包括电感 - 电容压控振荡器（LC VCO）。一个或多个后续层可以各自包括第二PLL，其可以包括自偏置（SB）VCO PLL或数字控制振荡器（DCO）PPL。随后的层可以相对于多个参数是可控的。可以基于可以被优先考虑的多个标准来评估和选择参数。例如可以选择参数以将相对于作为第一优先级的期望频率的容许偏差相等的频率误差最小化，将抖动减小为第二优先级，并将相对于期望频率的频率误差最小化为第三优先级。

2. 发明授权

US09698764B2 Quadrature divider 有权
公开(公告)号：US09698764B2
公开(公告)日：2017-07-04
申请号：US14127954
申请日：2013-09-18
申请人： Mark L. Neidengard , Qi Wang
发明人： Mark L. Neidengard , Qi Wang
IPC分类号： H03K3/037 , H03K5/15 , H03K23/58
CPC分类号： H03K3/037 , H03K5/15 , H03K23/588
摘要： Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus comprises: a first selection unit controllable by a clock signal, the first selection unit to directly or indirectly generate a first phase of the quadrature clock; a third selection unit controllable by the clock signal, the third selection unit to receive the first phase of the quadrature clock, the third selection unit to directly or indirectly generate a third phase of the quadrature clock, wherein the first selection unit to receive the third phase of the quadrature clock.

3. 发明授权

US07049865B2 Power-on detect circuit for use with multiple voltage domains 有权
标题翻译：上电检测电路用于多个电压域
公开(公告)号：US07049865B2
公开(公告)日：2006-05-23
申请号：US10794497
申请日：2004-03-05
申请人： Rachael J. Parker , Mark L. Neidengard , Patrick J. Ott , Gregory F. Taylor
发明人： Rachael J. Parker , Mark L. Neidengard , Patrick J. Ott , Gregory F. Taylor
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： Embodiments of the present invention include a circuit, a method, and a system for power-on detect circuitry for use with multiple voltage domains.
摘要翻译：本发明的实施例包括用于与多个电压域一起使用的上电检测电路的电路，方法和系统。

4. 发明申请

US20090322393A1 EDGE-TIMING ADJUSTMENT CIRCUIT 有权
标题翻译：边缘调整电路
公开(公告)号：US20090322393A1
公开(公告)日：2009-12-31
申请号：US12146663
申请日：2008-06-26
申请人： Mark L. Neidengard
发明人： Mark L. Neidengard
IPC分类号： H03K5/12
CPC分类号： H03K5/133 , G06F1/12 , H03K5/135 , H03K2005/00136
摘要： According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, output a tuned inverted falling clock signal via the second clock adjustment tuner, receive the inverted rising clock signal and the inverted falling clock signal at a clock synchronizer, output a synchronized tuned clock signal via the clock synchronizer, receive the synchronized tuned clock signal at a third clock adjustment tuner, and output a tuned clock signal. The first clock adjustment tuner and the second clock adjustment tuner provide coarser adjustments than the third clock adjustment tuner.
摘要翻译：根据一些实施例，提供了一种方法和系统，用于在第一时钟调整调谐器处接收时钟输入，在第二时钟调整调谐器处接收时钟输入，经由第一时钟调整调谐器输出经调谐的反相上升时钟信号，输出通过第二时钟调整调谐器调谐的倒置时钟信号，在时钟同步器处接收反相的上升时钟信号和反相的下降时钟信号，经由时钟同步器输出同步的调谐时钟信号，在第三时钟接收同步的调谐时钟信号调整调谐器，并输出调谐时钟信号。第一时钟调整调谐器和第二时钟调整调谐器提供比第三时钟调整调谐器更粗调的调整。

5. 发明授权

US07405631B2 Oscillating divider topology 有权
标题翻译：振荡分压器拓扑
公开(公告)号：US07405631B2
公开(公告)日：2008-07-29
申请号：US10880693
申请日：2004-06-30
申请人： Mark L. Neidengard
发明人： Mark L. Neidengard
IPC分类号： H03K3/03
CPC分类号： H04L7/0008 , G06F7/68 , H03K5/135
摘要： An oscillator includes a first circuit that asynchronously generates an oscillating signal in response to a second circuit of the oscillator acknowledging each cycle of the oscillating signal.
摘要翻译：振荡器包括第一电路，其响应于确认振荡信号的每个周期的振荡器的第二电路异步产生振荡信号。

6. 发明申请

US20070296467A1 Missing clock pulse detector 失效
标题翻译：缺少时钟脉冲检测器
公开(公告)号：US20070296467A1
公开(公告)日：2007-12-27
申请号：US11474025
申请日：2006-06-23
申请人： Mark L. Neidengard
发明人： Mark L. Neidengard
IPC分类号： H03K5/19
CPC分类号： H03K5/19 , H04L7/0008
摘要： A method to detect a missing a clock pulse is provided. The method begins by providing a clock signal and a delayed clock signal. The delayed clock signal is then sampled to generate a sample of the delayed clock signal. A missing clock pulse may be detected if the sample of the delayed clock signal does not equal an expected value of the delayed clock signal.
摘要翻译：提供了一种检测缺少时钟脉冲的方法。该方法从提供时钟信号和延迟的时钟信号开始。然后对延迟的时钟信号进行采样以产生延迟的时钟信号的采样。如果延迟的时钟信号的采样不等于延迟的时钟信号的期望值，则可以检测到丢失的时钟脉冲。

7. 发明申请

US20140266136A1 HYBRID DIGITAL PULSE WIDTH MODULATION (PWM) BASED ON PHASES OF A SYSTEM CLOCK 有权
标题翻译：基于系统时钟相位的混合数字脉宽调制（PWM）
公开(公告)号：US20140266136A1
公开(公告)日：2014-09-18
申请号：US14350547
申请日：2011-12-22
申请人： Harish K. Krishnamurthy , Annabelle Pratt , Mark L. Neidengard , George E. Matthew , James Alexander Darnes
发明人： Harish K. Krishnamurthy , Annabelle Pratt , Mark L. Neidengard , George E. Matthew , James Alexander Darnes
IPC分类号： H03K7/08 , H02M3/155
CPC分类号： H03K7/08 , H02M3/155 , H02M3/157
摘要： Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a D flip-flop under control of a selected phase of the system clock. Alternatively, a target count may be derived from the duty command, and an edge of the PWM pulse may be initiated when a count of the selected phase equals the target count. The pulse edge may be registered by a D flip-flop to a SR flip-flop under control of the selected phase. The phases of the system clock may be shared amongst multiple systems to generate multiple PWM signals. A system may include a DLL and digital logic, which may consist essentially of combinational logic and registers.
摘要翻译：可以基于前沿调制（LEM），后沿调制（TEM）和/或双边缘调制实现基于系统时钟的可选相位的脉宽调制（PWM）。可以基于与系统时钟同步的占空指令来产生初始脉冲，并且可以在系统时钟的所选相位的控制下向D触发器注册。或者，可以从占空指令导出目标计数，并且当所选择的相位的计数等于目标计数时，可以启动PWM脉冲的边沿。在所选相位的控制下，脉冲沿可由D触发器寄存至SR触发器。系统时钟的相位可以在多个系统之间共享以产生多个PWM信号。系统可以包括DLL和数字逻辑，其可以主要由组合逻辑和寄存器组成。

8. 发明申请

US20130086410A1 FREQUENCY SYNTHESIS METHODS AND SYSTEMS 有权
标题翻译：频率合成方法和系统
公开(公告)号：US20130086410A1
公开(公告)日：2013-04-04
申请号：US13251220
申请日：2011-10-01
申请人： Nasser A. Kurd , Robert J. Greiner , Mark L. Neidengard , Vaughn J. Grossnickle
发明人： Nasser A. Kurd , Robert J. Greiner , Mark L. Neidengard , Vaughn J. Grossnickle
IPC分类号： G06F1/12 , H03L7/08
CPC分类号： H03L7/23 , G06F1/08 , H03L7/183
摘要： Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.
摘要翻译：综合参考频率的多层方法和系统，并根据多个优先级标准控制一层或多层。频率合成器的第一层可以包括第一锁相环（PLL），其可以包括电感 - 电容压控振荡器（LC VCO）。一个或多个后续层可以各自包括第二PLL，其可以包括自偏置（SB）VCO PLL或数字控制振荡器（DCO）PPL。随后的层可以相对于多个参数是可控的。可以基于可以被优先考虑的多个标准来评估和选择参数。例如可以选择参数以将相对于作为第一优先级的期望频率的容许偏差相等的频率误差最小化，将抖动减小为第二优先级，并将相对于期望频率的频率误差最小化为第三优先级。

9. 发明授权

US07679404B2 Missing clock pulse detector 失效
标题翻译：缺少时钟脉冲检测器
公开(公告)号：US07679404B2
公开(公告)日：2010-03-16
申请号：US11474025
申请日：2006-06-23
申请人： Mark L. Neidengard
发明人： Mark L. Neidengard
IPC分类号： H03K5/19
CPC分类号： H03K5/19 , H04L7/0008
摘要： A method to detect a missing a clock pulse is provided. The method begins by providing a clock signal and a delayed clock signal. The delayed clock signal is then sampled to generate a sample of the delayed clock signal. A missing clock pulse may be detected if the sample of the delayed clock signal does not equal an expected value of the delayed clock signal.
摘要翻译：提供了一种检测缺少时钟脉冲的方法。该方法从提供时钟信号和延迟的时钟信号开始。然后对延迟的时钟信号进行采样以产生延迟的时钟信号的采样。如果延迟的时钟信号的采样不等于延迟的时钟信号的期望值，则可以检测到丢失的时钟脉冲。

10. 发明申请

US20160285436A1 QUADRATURE DIVIDER 有权
标题翻译：四分法师
公开(公告)号：US20160285436A1
公开(公告)日：2016-09-29
申请号：US14127954
申请日：2013-09-18
申请人： Mark L. NEIDENGARD , Qi WANG
发明人： Mark L. NEIDENGARD , Qi WANG
IPC分类号： H03K3/037
CPC分类号： H03K3/037 , H03K5/15 , H03K23/588
摘要： Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus comprises: a first selection unit controllable by a clock signal, the first selection unit to directly or indirectly generate a first phase of the quadrature clock; a third selection unit controllable by the clock signal, the third selection unit to receive the first phase of the quadrature clock, the third selection unit to directly or indirectly generate a third phase of the quadrature clock, wherein the first selection unit to receive the third phase of the quadrature clock.
摘要翻译：描述了正交分频器的装置。该装置独立于卡锁锁存器，并且用于产生正交时钟。该装置包括：由时钟信号控制的第一选择单元，第一选择单元直接或间接产生正交时钟的第一相位; 由所述时钟信号控制的第三选择单元，所述第三选择单元接收所述正交时钟的所述第一相位，所述第三选择单元直接或间接产生所述正交时钟的第三相位，其中所述第一选择单元接收所述第三选择单元，正交时钟的相位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式