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1. 发明授权

US08399937B2 Semiconductor body and method for the design of a semiconductor body with a connecting line 有权
标题翻译：用于设计具有连接线的半导体主体的半导体本体和方法
公开(公告)号：US08399937B2
公开(公告)日：2013-03-19
申请号：US12447185
申请日：2007-10-24
申请人： Georg Röhrer , Martin Knaipp
发明人： Georg Röhrer , Martin Knaipp
IPC分类号： H01L23/48
CPC分类号： H01L29/41758 , H01L23/4824 , H01L24/36 , H01L29/78 , H01L29/8611 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01052 , H01L2924/01061 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A semiconductor body (1) comprises a connecting lead (21) for contacting a semiconductor area (2). The conductivity S per unit length of the connecting lead (21) changes from a first value SW to a second value S0. The semiconductor area (2) is electrically conductively connected to the connecting lead (21).
摘要翻译：半导体本体（1）包括用于接触半导体区域（2）的连接引线（21）。连接引线（21）的每单位长度的电导率S从第一值SW变为第二值S0。半导体区域（2）与导线（21）导电连接。

2. 发明授权

US07977197B2 Method for fabricating a transistor with reliable source doping 有权
标题翻译：用于制造具有可靠的源掺杂的晶体管的方法
公开(公告)号：US07977197B2
公开(公告)日：2011-07-12
申请号：US12083169
申请日：2006-10-06
申请人： Martin Knaipp , Georg Röhrer
发明人： Martin Knaipp , Georg Röhrer
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L29/1033 , H01L29/1087 , H01L29/66681 , H01L29/7816
摘要： A transistor and a method for the fabrication of transistors with different gate oxide thicknesses is proposed, in which for the doping of the source, the typical LDD implantation, which is formed after the fabrication of the gate electrode, is replaced by a doping step, which is generated before applying the gate stack. In this way that is already a component of the remaining process sequence in the fabrication of the transistor doping can be used.
摘要翻译：提出了用于制造具有不同栅极氧化物厚度的晶体管的晶体管和方法，其中对于掺杂源，在栅电极制造之后形成的典型LDD注入被掺杂步骤代替，其在施加栅极堆叠之前产生。以这种方式，可以使用晶体管掺杂制造中剩余工艺序列的一个组成部分。

3. 发明授权

US09093527B2 High-voltage transistor and component containing the latter 有权
标题翻译：高压晶体管和含有后者的元件
公开(公告)号：US09093527B2
公开(公告)日：2015-07-28
申请号：US12085203
申请日：2006-11-13
申请人： Martin Knaipp , Georg Röhrer
发明人： Martin Knaipp , Georg Röhrer
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/423
CPC分类号： H01L29/7835 , H01L29/0638 , H01L29/1041 , H01L29/105 , H01L29/42368 , H01L29/4238 , H01L29/7833
摘要： A high-voltage NMOS transistor with low threshold voltage. The body doping that defines the channel region is in the form of a deep p-well. An additional shallow p-doping is arranged as a channel stopper on the transistor head. This additional shallow p-doping is produced in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and extends up to a location underneath a field oxide region that encloses the active window. The leakage current of the parasitic transistor at the transistor head is suppressed with the channel stopper.
摘要翻译：具有低阈值电压的高压NMOS晶体管。限定通道区域的体掺杂是深p阱的形式。在晶体管头上布置作为沟道阻挡层的另外的浅p掺杂。这种额外的浅p掺杂是在远离沟道区的深p阱的末端的半导体衬底中产生的，并且延伸到包围有源窗口的场氧化物区域下方的位置。晶体管头上的寄生晶体管的漏电流被通道阻塞抑制。

4. 发明申请

US20100117162A1 Semiconductor Body and Method for the Design of a Semiconductor Body with a Connecting Line 有权
标题翻译：具有连接线的半导体器件的半导体器件和方法
公开(公告)号：US20100117162A1
公开(公告)日：2010-05-13
申请号：US12447185
申请日：2007-10-24
申请人： Georg Röhrer , Martin Knaipp
发明人： Georg Röhrer , Martin Knaipp
IPC分类号： H01L23/48 , H01L29/78 , H01L29/861 , G06F17/50
CPC分类号： H01L29/41758 , H01L23/4824 , H01L24/36 , H01L29/78 , H01L29/8611 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01052 , H01L2924/01061 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A semiconductor body (1) comprises a connecting lead (21) for contacting a semiconductor area (2). The conductivity S per unit length of the connecting lead (21) changes from a first value SW to a second value S0. The semiconductor area (2) is electrically conductively connected to the connecting lead (21).
摘要翻译：半导体本体（1）包括用于接触半导体区域（2）的连接引线（21）。连接引线（21）的每单位长度的电导率S从第一值SW变为第二值S0。半导体区域（2）与导线（21）导电连接。

5. 发明授权

US07663203B2 High-voltage PMOS transistor 有权
标题翻译：高压PMOS晶体管
公开(公告)号：US07663203B2
公开(公告)日：2010-02-16
申请号：US10591001
申请日：2005-02-28
申请人： Martin Knaipp
发明人： Martin Knaipp
IPC分类号： H01L29/94
CPC分类号： H01L21/266 , H01L29/0615 , H01L29/0847 , H01L29/1079 , H01L29/402 , H01L29/66659 , H01L29/7835
摘要： In a high-voltage PMOS transistor having an insulated gate electrode (18), a p-conductive source (15) in an n-conductive well (11), a p-conductive drain (14) in a p-conductive well (12) which is arranged in the n-conductive well, and having a field oxide area (13) between the gate electrode and drain, the depth (A′-B′) of the n-conductive well underneath the drain (14) is less than underneath the source (15), and the depth (A′-B′) of the p-conductive well is greatest underneath the drain (14).
摘要翻译：在具有绝缘栅电极（18）的高电压PMOS晶体管中，n导电阱（11）中的p导电源（15），p导电阱（12）中的p导电漏极（14）），并且在栅电极和漏极之间具有场氧化物区域（13），漏极（14）下方的n导电阱的深度（A'-B'）较小（15）下方，并且p导电阱的深度（A'-B'）在漏极（14）的下面是最大的。

6. 发明申请

US20090212360A1 High-Voltage Transistor and Method for its Manufacture 有权
标题翻译：高压晶体管及其制造方法
公开(公告)号：US20090212360A1
公开(公告)日：2009-08-27
申请号：US11992172
申请日：2005-09-20
申请人： Martin Knaipp
发明人： Martin Knaipp
IPC分类号： H01L29/772 , H01L21/265
CPC分类号： H01L29/7816 , H01L21/26586 , H01L21/266 , H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L21/823892 , H01L29/0638 , H01L29/0847 , H01L29/0878 , H01L29/105 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A high-voltage transistor is provided with a well of a first conductivity type, which is arranged in a substrate (10) of a second conductivity type, with a source (14), a drain (12), and a gate electrode (18) above a channel region (KN, KP) formed between the source and the drain, wherein several staggered and nested wells (11, 13, 15, 17) of the same conductivity type extend from the source (14) or the drain (12) into the substrate (10) and wherein the doping concentration (log c) of the wells essentially decreases and is smoothed from the substrate surface with increasing depth (T) and also laterally. In this way, field-strength increases and also unintentional breakdown are prevented. Furthermore, a production method is specified.
摘要翻译：高压晶体管设置有第一导电类型的阱，其布置在第二导电类型的衬底（10）中，源极（14），漏极（12）和栅电极（18））在源极和漏极之间形成的沟道区（KN，KP）之上，其中相同导电类型的几个交错和嵌套阱（11,13,15,17）从源极（14）或漏极（12）延伸）到基底（10）中，并且其中孔的掺杂浓度（log c）基本上减小，并且随着深度（T）增加而且从侧向延伸到基底表面。这样就可以防止场强增加，而且无意破坏。此外，规定了制造方法。

7. 发明申请

US20140361374A1 HIGH-VOLTAGE TRANSISTOR DEVICE AND PRODUCTION METHOD 有权
标题翻译：高压晶体管器件和生产方法
公开(公告)号：US20140361374A1
公开(公告)日：2014-12-11
申请号：US14234364
申请日：2012-07-06
申请人： Martin Knaipp
发明人： Martin Knaipp
IPC分类号： H01L27/088 , H01L29/08 , H01L29/10 , H01L21/265 , H01L21/8234 , H01L29/40
CPC分类号： H01L27/088 , H01L21/265 , H01L21/823418 , H01L21/823493 , H01L27/0922 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/66659 , H01L29/7835
摘要： The high-voltage transistor device has a p-type semiconductor substrate (1) that is furnished with a p-type epitaxial layer (2). A well (3) and a body region (4) are located in the epitaxial layer. A source region (5) is arranged in the body region, and a drain region (6) is arranged in the well. A channel region (7) is located in the body region between the well and the source region. A gate electrode (8) is arranged above the channel region. In the part of the semiconductor substrate and the epitaxial layer underneath the source region and the channel region, a deep body region (11) is present, which has a higher dopant concentration in comparison to the remainder of the semiconductor substrate.
摘要翻译：高压晶体管器件具有配备有p型外延层（2）的p型半导体衬底（1）。阱（3）和体区（4）位于外延层中。源区域（5）布置在体区域中，并且漏极区域（6）布置在井中。通道区域（7）位于阱和源极区域之间的体区中。栅电极（8）布置在通道区域的上方。在半导体衬底和源极区域和沟道区域下面的外延层的部分中，存在与半导体衬底的其余部分相比较高掺杂剂浓度的深体区域（11）。

8. 发明授权

US07898030B2 High-voltage NMOS-transistor and associated production method 有权
标题翻译：高压NMOS晶体管及相关生产方法
公开(公告)号：US07898030B2
公开(公告)日：2011-03-01
申请号：US11659512
申请日：2005-08-05
申请人： Martin Knaipp , Jong Mun Park
发明人： Martin Knaipp , Jong Mun Park
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7816
摘要： An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (1). A lateral junction (11) between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path (14) in the vicinity of the drain region (3) so as to avoid a high voltage drop in the channel region (13) during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.
摘要翻译：深导电阱（DP）中的n导电掺杂源区（2），沟道区（13），由反掺杂区（12）形成的漂移区（14），优选地在栅极场板 6），栅极氧化物（8）绝缘，并且布置在深导电阱（DN）中的n导电掺杂漏极区域（3）依次布置在衬底（1）的顶侧。深沟道阱（DP）和深导通阱（DN）之间的横向结（11）存在于漏极区域（3）附近的漂移路径（14）中，以避免在晶体管工作期间，沟道区域（13）中的高电压降，以及在源极和漏极之间实现高阈值电压以及高的击穿电压。

9. 发明授权

US07888234B2 Method for manufacturing a semiconductor body with a trench and semiconductor body with a trench 有权
标题翻译：制造具有沟槽的半导体本体和具有沟槽的半导体本体的方法
公开(公告)号：US07888234B2
公开(公告)日：2011-02-15
申请号：US12148446
申请日：2008-04-17
申请人： Martin Knaipp , Bernhard Löffler
发明人： Martin Knaipp , Bernhard Löffler
IPC分类号： H01L21/76
CPC分类号： H01L21/76235 , H01L21/76205
摘要： A method for manufacturing a semiconductor body with a trench comprises the steps of etching the trench (11) in the semiconductor body (10) and forming a silicon oxide layer (12) on at least one side wall (14) of the trench (11) and on the bottom (15) of the trench (11) by means of thermal oxidation. Furthermore, the silicon oxide layer (12) on the bottom (15) of the trench (11) is removed and the trench (11) is filled with polysilicon that forms a polysilicon body (13).
摘要翻译：用于制造具有沟槽的半导体本体的方法包括以下步骤：蚀刻半导体本体（10）中的沟槽（11）并在沟槽（11）的至少一个侧壁（14）上形成氧化硅层）并且通过热氧化在沟槽（11）的底部（15）上。此外，除去沟槽（11）的底部（15）上的氧化硅层（12），并且用形成多晶硅体（13）的多晶硅填充沟槽（11）。

10. 发明申请

US20090321822A1 HIGH-VOLTAGE TRANSISTOR WITH IMPROVED HIGH STRIDE PERFORMANCE 有权
标题翻译：具有改进的高扭矩性能的高压晶体管
公开(公告)号：US20090321822A1
公开(公告)日：2009-12-31
申请号：US12299741
申请日：2007-04-16
申请人： Martin Knaipp , Georg Röhrer , Jong Mun Park
发明人： Martin Knaipp , Georg Röhrer , Jong Mun Park
IPC分类号： H01L29/78
CPC分类号： H01L29/0886 , H01L21/266 , H01L29/0619 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/7816
摘要： A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible.
摘要翻译：公开了一种高压NMOS晶体管，其中p掺杂体通过具有夹紧区域的DN阱与p掺杂衬底隔离，其中DN阱的深度为最小。由于空隙电荷区域在夹断区域接触源极和漏极之间的场氧化物，所以通过在提高漏极电位的形成空间电荷区域产生漏极电位的屏蔽。可以在增强的电压电平的高端进行操作。

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