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    • 5. 发明授权
    • MOS transistor and semiconductor integrated circuit
    • MOS晶体管和半导体集成电路
    • US07847324B2
    • 2010-12-07
    • US12336785
    • 2008-12-17
    • Masaki Kasahara
    • Masaki Kasahara
    • H01L29/76H01L21/70
    • H01L27/0207H01L29/1087H01L29/41758
    • A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells, plural boundaries that are parallel to the plural transistor cells, and plural back gates arranged at the plural boundaries, each of the plural transistor cell blocks has two boundaries of the plural boundaries, wherein the plural transistor cells have a substantially striped shape, and each of the plural transistor cell blocks includes: at least one drain; plural sources; and plural extended gates, wherein each of the plural transistor cells is formed from one of the plural extended gates sandwiched by one of at least one drain and one of the plural sources, one of the plural sources is adjacent to one of two boundaries, and another one of the plural sources is adjacent to another one of two boundaries.
    • MOS晶体管包括彼此相邻并排布置的多个晶体管单元块,其中多个晶体管单元块被配置为具有多个晶体管单元,与多个晶体管单元平行的多个边界,以及布置在多个边界的多个后栅 所述多个晶体管单元块中的每一个具有所述多个边界的两个边界,其中所述多个晶体管单元具有大致条形形状,并且所述多个晶体管单元块中的每一个包括:至少一个漏极; 复数来源 以及多个扩展栅极,其中,所述多个晶体管单元中的每一个由所述多个延伸栅极中的至少一个漏极和所述多个源中的一个形成,所述多个源极中的一个与所述多个源中的一个源极相邻, 多个来源中的另一个与两个边界中的另一个相邻。
    • 8. 发明授权
    • Domed compressed tampons
    • 圆顶压缩棉塞
    • US6003216A
    • 1999-12-21
    • US829369
    • 1997-03-31
    • Raymond J. Hull, Jr.Gerd R. RexWilfried BaerMasaki KasaharaToshio Sonoda
    • Raymond J. Hull, Jr.Gerd R. RexWilfried BaerMasaki KasaharaToshio Sonoda
    • A61F13/22A61F13/20
    • B30B11/007A61F13/2085Y10S604/904
    • An improved apparatus and method compresses a cylindrical blank into a tampon which is dimensionally stable and which is provided with a domed insertion end. A cylindrical blank is radially compressed and then introduced into a cylindrical axial compression chamber. The blank is then subjected to an extreme axial overcompression. The closed insertion end of the compression chamber has a bore formed therethrough. The bore is generally coaxial and is adapted to accept a reciprocating ejection ram having a ram surface facing into the chamber. When the ram is seated in the first position, the ram surface and the insertion end wall of the compression chamber together form a smooth doming surface. The bore periphery is of a smaller diameter than the chamber and hence radially spaced from the side walls of the chamber, and the ram has sufficient clearance to move through the chamber and eject the tampon without interference from the walls of the chamber.
    • 改进的装置和方法将圆柱形坯料压缩成尺寸稳定的棉塞,并且设置有圆顶插入端。 圆柱形坯料被径向压缩,然后引入圆柱形轴向压缩室。 然后坯料经受极端的轴向过压。 压缩室的封闭插入端具有通过其形成的孔。 孔通常是同轴的,并且适于接受具有面向腔室的冲头表面的往复式排出冲头。 当冲头位于第一位置时,压头室的压头表面和插入端壁一起形成平滑的圆顶表面。 孔周边具有比腔室更小的直径,并且因此与腔室的侧壁径向间隔开,并且冲头具有足够的间隙以移动通过腔室并且弹出卫生棉条而不受室的壁的干扰。
    • 9. 发明申请
    • MOS Transistor and Semiconductor Integrated Circuit
    • MOS晶体管和半导体集成电路
    • US20090166756A1
    • 2009-07-02
    • US12336785
    • 2008-12-17
    • Masaki Kasahara
    • Masaki Kasahara
    • H01L29/94
    • H01L27/0207H01L29/1087H01L29/41758
    • A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells, plural boundaries that are parallel to the plural transistor cells, and plural back gates arranged at the plural boundaries, each of the plural transistor cell blocks has two boundaries of the plural boundaries, wherein the plural transistor cells have a substantially striped shape, and each of the plural transistor cell blocks includes: at least one drain; plural sources; and plural extended gates, wherein each of the plural transistor cells is formed from one of the plural extended gates sandwiched by one of at least one drain and one of the plural sources, one of the plural sources is adjacent to one of two boundaries, and another one of the plural sources is adjacent to another one of two boundaries.
    • MOS晶体管包括彼此相邻并排布置的多个晶体管单元块,其中多个晶体管单元块被配置为具有多个晶体管单元,与多个晶体管单元平行的多个边界,以及布置在多个边界的多个后栅 所述多个晶体管单元块中的每一个具有所述多个边界的两个边界,其中所述多个晶体管单元具有大致条形形状,并且所述多个晶体管单元块中的每一个包括:至少一个漏极; 复数来源 以及多个扩展栅极,其中,所述多个晶体管单元中的每一个由所述多个延伸栅极中的至少一个漏极和所述多个源中的一个形成,所述多个源极中的一个与所述多个源中的一个相邻,所述多个源中的一个与两个边界中的一个相邻, 多个来源中的另一个与两个边界中的另一个相邻。