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1. 发明申请

US20170346095A1 POLYTHIOPHENE DERIVATIVE, METHOD FOR PRODUCING SAME, POSITIVE ELECTRODE ACTIVE MATERIAL FOR SECONDARY BATTERIES, AND SECONDARY BATTERY 有权
公开(公告)号：US20170346095A1
公开(公告)日：2017-11-30
申请号：US15106562
申请日：2015-01-13
申请人： Masayoshi NOMURA
发明人： Masayoshi NOMURA
IPC分类号： H01M4/60 , C08G61/12 , H01M10/0565 , H01M4/02
CPC分类号： H01M4/608 , C08G61/126 , C08G2261/122 , C08G2261/1424 , C08G2261/145 , C08G2261/312 , C08G2261/3223 , C08G2261/43 , C08G2261/514 , H01L51/0036 , H01L51/0043 , H01M10/0565 , H01M2004/028
摘要： A polythiophene derivative including a repeating unit represented by General Formula (1) below: where R1 and R2 each independently denote a group having from 2 through 9 carbon atoms represented by —(R3—S)p—R4 (where R3 denotes an alkylene group having from 1 through 4 carbon atoms, R4 denotes an alkyl group having from 1 through 6 carbon atoms or an aromatic group having from 5 through 6 carbon atoms, and p denotes an integer of 1 or 2), Ar denotes an optionally substituted divalent or monovalent aromatic ring moiety or aromatic heterocyclic moiety, m denotes a natural number of 2 or more, and n denotes a natural number of 0 or 2 or more.

2. 发明申请

US20170158810A1 POLYTHIOPHENE DERIVATIVE, SECONDARY CELL POSITIVE ELECTRODE ACTIVE MATERIAL, AND SECONDARY CELL 审中-公开
公开(公告)号：US20170158810A1
公开(公告)日：2017-06-08
申请号：US15435883
申请日：2017-02-17
申请人： Masayoshi NOMURA
发明人： Masayoshi NOMURA
IPC分类号： C08G61/12 , H01M4/60 , H01M10/0525
CPC分类号： C08G61/126 , C08G61/12 , C08G2261/11 , C08G2261/1424 , C08G2261/145 , C08G2261/146 , C08G2261/148 , C08G2261/3243 , H01M4/60 , H01M4/608 , H01M10/0525
摘要： Provided is a polythiophene derivative including a repeating unit represented by general formula (1) below. In general formula (1), Z represents a group of atoms forming a 5- through 9-membered heterocycle containing a chalcogen element as a ring member. When the group of atoms contains a plurality of chalcogen elements, the kinds of the chalcogen elements may be the same or different. Ar represents an aromatic ring or aromatic heterocycle that may contain a substituent. n represents a natural number of 2 or greater. m represents 0 or a natural number of 2 or greater.

3. 发明申请

US20170110732A1 SECONDARY CELL 审中-公开
公开(公告)号：US20170110732A1
公开(公告)日：2017-04-20
申请号：US15289502
申请日：2016-10-10
申请人： Masayoshi NOMURA
发明人： Masayoshi NOMURA
IPC分类号： H01M4/60 , H01M10/0525
CPC分类号： H01M4/606 , H01M10/0525
摘要： To provide a secondary cell including an electrode active material that is a compound represented by General Formula (1) below: where n is a natural number of from 4 through 8, a is a natural number of from 1 through 4, R1 and R2 may be identical to or different from each other and are each a hydrogen atom, an alkyl group, or an aromatic hydrocarbon group that may have a substituent, Y is a substituent, and b is an integer of from 0 through 3 and a+b is 4 or less in General Formula (1).

4. 外观设计

USD739339S1 Tire tread 有权
公开(公告)号：USD739339S1
公开(公告)日：2015-09-22
申请号：US29513551
申请日：2015-01-02
申请人： Masayoshi Nomura , Julien Besset , Mathieu Vandaele
设计人： Masayoshi Nomura , Julien Besset , Mathieu Vandaele

5. 外观设计

USD735655S1 Surface design for a pneumatic tire 有权
公开(公告)号：USD735655S1
公开(公告)日：2015-08-04
申请号：US29477095
申请日：2013-12-19
申请人： Arnaud Frappart , Masayoshi Nomura
设计人： Arnaud Frappart , Masayoshi Nomura

6. 发明授权

US08737155B2 Power saving memory apparatus, systems, and methods 有权
标题翻译：省电存储装置，系统和方法
公开(公告)号：US08737155B2
公开(公告)日：2014-05-27
申请号：US13213949
申请日：2011-08-19
申请人： Yutaka Ito , Masayoshi Nomura , Keiichiro Abe
发明人： Yutaka Ito , Masayoshi Nomura , Keiichiro Abe
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/147 , G11C5/148 , G11C7/20 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C2211/4067 , G11C2211/4068
摘要： Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括电压发生器，用于产生电压以施加到用于访问存储器件的存储器单元的线，其中在存储器单元未被访问时将电压施加到线路;以及功率控制器，电压在存储器件的刷新操作之后的时间间隔期间改变。公开了包括附加装置，系统和方法的其它实施例。

7. 发明授权

US08122304B2 JTAG controlled self-repair after packaging 有权
公开(公告)号：US08122304B2
公开(公告)日：2012-02-21
申请号：US12906764
申请日：2010-10-18
申请人： Yoshinori Fujiwara , Masayoshi Nomura
发明人： Yoshinori Fujiwara , Masayoshi Nomura
IPC分类号： G11C29/00 , G01R31/28 , G11C17/18
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.

8. 发明申请

US20110273185A1 METHODS FOR DEFECT TESTING OF EXTERNALLY ACCESSIBLE INTEGRATED CIRCUIT INTERCONNECTS 有权
标题翻译：外部可访问集成电路互连的缺陷测试方法
公开(公告)号：US20110273185A1
公开(公告)日：2011-11-10
申请号：US13183931
申请日：2011-07-15
申请人： Yoshinori Fujiwara , Masayoshi Nomura
发明人： Yoshinori Fujiwara , Masayoshi Nomura
IPC分类号： G01R31/04
CPC分类号： G01R31/31715 , G01R31/3004 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/56 , G11C2029/5006
摘要： Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.
摘要翻译：装置和方法在集成电路中提供内置的测试增强功能。这些测试增强允许例如对多于一个焊盘的焊盘和/或泄漏电流测试的连续性测试。所公开的技术可以允许在芯片级别对集成电路进行更彻底的测试，从而减少进一步处理的缺陷设备的数量，从而节省时间和金钱。在一个实施例中，测试信号通过内置路径实时路由，该内置路径包括用于待测焊盘的输入缓冲器。这允许测试焊盘和输入缓冲器之间的连续性。输出缓冲区也可以根据需要进行测试。在另一个实施例中，管芯的两个或更多个焊盘电子耦合在一起，使得由连接到一个焊盘的探头施加的泄漏电流测试可用于测试另一焊盘。

9. 发明授权

US08004920B2 Power saving memory apparatus, systems, and methods 有权
标题翻译：省电存储装置，系统和方法
公开(公告)号：US08004920B2
公开(公告)日：2011-08-23
申请号：US11754756
申请日：2007-05-29
申请人： Yutaka Ito , Masayoshi Nomura , Keiichiro Abe
发明人： Yutaka Ito , Masayoshi Nomura , Keiichiro Abe
IPC分类号： G11C5/14 , G11C7/22
CPC分类号： G11C5/14 , G11C5/147 , G11C5/148 , G11C7/20 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C2211/4067 , G11C2211/4068
摘要： Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括电压发生器，用于产生电压以施加到用于访问存储器件的存储器单元的线，其中在存储器单元未被访问时将电压施加到线路;以及功率控制器，电压在存储器件的刷新操作之后的时间间隔期间改变。公开了包括附加装置，系统和方法的其它实施例。

10. 发明授权

US07990163B2 Systems and methods for defect testing of externally accessible integrated circuit interconnects 有权
标题翻译：外部可访问的集成电路互连的缺陷测试系统和方法
公开(公告)号：US07990163B2
公开(公告)日：2011-08-02
申请号：US12570138
申请日：2009-09-30
申请人： Yoshinori Fujiwara , Masayoshi Nomura
发明人： Yoshinori Fujiwara , Masayoshi Nomura
IPC分类号： G01R31/02
CPC分类号： G01R31/31715 , G01R31/3004 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/56 , G11C2029/5006
摘要： Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.
摘要翻译：装置和方法在集成电路中提供内置的测试增强功能。这些测试增强允许例如对多于一个焊盘的焊盘和/或泄漏电流测试的连续性测试。所公开的技术可以允许在芯片级别对集成电路进行更彻底的测试，从而减少进一步处理的缺陷设备的数量，从而节省时间和金钱。在一个实施例中，测试信号通过内置路径实时路由，该内置路径包括用于待测焊盘的输入缓冲器。这允许测试焊盘和输入缓冲器之间的连续性。输出缓冲区也可以根据需要进行测试。在另一个实施例中，管芯的两个或更多焊盘电耦合在一起，使得由连接到一个焊盘的探头施加的泄漏电流测试可用于测试另一焊盘。

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