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1. 发明授权

US09268720B2 Load balancing scheme in multiple channel DRAM systems 有权
标题翻译：多通道DRAM系统中的负载均衡方案
公开(公告)号：US09268720B2
公开(公告)日：2016-02-23
申请号：US12872282
申请日：2010-08-31
申请人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
发明人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F13/1647 , G06F12/0607 , G06F13/1642 , G06F13/1657 , G06F2213/0064
摘要： A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.
摘要翻译：多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。内存通道的访问由内存控制器控制。总线主机通过互连系统耦合到存储器控制器，并且存储器请求从总线主机传送到存储器控制器。如果在存储器通道中检测到拥塞，则产生拥塞信号并将其发送到总线主机。因此，基于拥塞信号，存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。

2. 发明授权

US08719610B2 Low power electronic system architecture using non-volatile magnetic memory 有权
标题翻译：低功耗电子系统架构采用非易失性磁记忆体
公开(公告)号：US08719610B2
公开(公告)日：2014-05-06
申请号：US12235933
申请日：2008-09-23
申请人： Matthew Michael Nowak , Lew Chua-Eoan , Seung H Kang
发明人： Matthew Michael Nowak , Lew Chua-Eoan , Seung H Kang
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3275 , G11C11/16 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit.
摘要翻译：计算系统包括耦合到至少一个功能单元的至少一个功能单元和磁随机存取存储器（MRAM）块。 MRAM块被配置为在所述至少一个功能单元的掉电状态期间存储所述至少一个功能单元的功能状态。

3. 发明授权

US08492874B2 High density metal-insulator-metal trench capacitor 有权
标题翻译：高密度金属 - 绝缘体 - 金属沟槽电容器
公开(公告)号：US08492874B2
公开(公告)日：2013-07-23
申请号：US13021151
申请日：2011-02-04
申请人： Je-Hsiung Lan , Matthew Michael Nowak , Evgeni P. Gousev , Jonghae Kim , Clarence Chui
发明人： Je-Hsiung Lan , Matthew Michael Nowak , Evgeni P. Gousev , Jonghae Kim , Clarence Chui
IPC分类号： H01G4/10 , H01G4/12 , H01L23/5222 , H01L28/82 , H01L29/945 , H01L23/642
CPC分类号： H01L28/82 , H01G4/012 , H01G4/10 , H01L23/5223 , H01L23/642 , H01L28/87 , H01L29/945 , H01L2224/16225 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311
摘要： Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.
摘要翻译：通过增加电容器的表面积来实现更高的电容密度。可以通过在半导体管芯上的沟槽中形成各向同性球形（凹面）来获得更大的表面积。通过沉积非晶硅和氧化硅的双层来制造凹面。在用于沟槽的氧化硅硬掩模中图案化开口。通过各向同性蚀刻将开口转移到非晶硅层以形成凹面。导电，绝缘和导电层通过原子层沉积沉积在沟槽的凹面上。

4. 发明申请

US20120054455A1 Non-Uniform Interleaving Scheme In Multiple Channel DRAM System 审中-公开
标题翻译：多通道DRAM系统中的非均匀交织方案
公开(公告)号：US20120054455A1
公开(公告)日：2012-03-01
申请号：US12872458
申请日：2010-08-31
申请人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
发明人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
IPC分类号： G06F12/06
CPC分类号： G06F13/1647 , G06F12/0607
摘要： A non-uniform interleaving scheme in a multiple channel DRAM system comprises associating memory data with a memory address, associating address zones to predetermined ranges of memory addresses and associating predetermined interleaving granularities with the address zones. Memory data is interleaved across two or more memory channels such that a predetermined interleaving granularity is applied to each address zone.
摘要翻译：多通道DRAM系统中的非均匀交织方案包括将存储器数据与存储器地址相关联，将地址区域与预定范围的存储器地址相关联，并将预定的交织粒度与地址区域相关联。存储器数据在两个或更多个存储器通道之间交错，使得预定的交织粒度被应用于每个地址区。

5. 发明申请

US20110320698A1 Multi-Channel Multi-Port Memory 有权
标题翻译：多通道多端口存储器
公开(公告)号：US20110320698A1
公开(公告)日：2011-12-29
申请号：US12823515
申请日：2010-06-25
申请人： Feng Wang , Shiqun Gu , Matthew Michael Nowak
发明人： Feng Wang , Shiqun Gu , Matthew Michael Nowak
IPC分类号： G06F12/00
CPC分类号： G06F13/1663
摘要： A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels.
摘要翻译：公开了一种多通道多端口存储器。在特定实施例中，多通道存储器包括响应于多个存储器控制器的多个通道。多通道存储器还可以包括可由第一组多个通道访问的第一多端口多存储体结构和可由第二组多个通道访问的第二多端口多存储体结构。

6. 发明申请

US20130222060A1 MUTUALLY COUPLED MATCHING NETWORK 审中-公开
标题翻译： MUTUALLY耦合匹配网络
公开(公告)号：US20130222060A1
公开(公告)日：2013-08-29
申请号：US13406431
申请日：2012-02-27
申请人： Chi Shun Lo , Jonghae Kim , Wesley Nathaniel Allen , Chengjie Zuo , Changhan Yun , Thomas Andrew Myers , Prasad Srinivasa Siva Gudem , Matthew Michael Nowak
发明人： Chi Shun Lo , Jonghae Kim , Wesley Nathaniel Allen , Chengjie Zuo , Changhan Yun , Thomas Andrew Myers , Prasad Srinivasa Siva Gudem , Matthew Michael Nowak
IPC分类号： H03H7/38 , H03F1/00
CPC分类号： H03H7/38 , H03H7/09
摘要： An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit.
摘要翻译：公开了一种阻抗匹配电路。阻抗匹配电路包括两个或更多个相互耦合的电感器。阻抗匹配电路的总自感小于包括不相互耦合的电感器的对应阻抗匹配电路。两个或更多个相互耦合的电感器可以具有与相应的阻抗匹配电路中的电流比匹配的已知电流比。

7. 发明授权

US08380940B2 Multi-channel multi-port memory 有权
标题翻译：多通道多端口存储器
公开(公告)号：US08380940B2
公开(公告)日：2013-02-19
申请号：US12823515
申请日：2010-06-25
申请人： Feng Wang , Shiqun Gu , Matthew Michael Nowak
发明人： Feng Wang , Shiqun Gu , Matthew Michael Nowak
IPC分类号： G06F12/06
CPC分类号： G06F13/1663
摘要： A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels.
摘要翻译：公开了一种多通道多端口存储器。在特定实施例中，多通道存储器包括响应于多个存储器控制器的多个通道。多通道存储器还可以包括可由第一组多个通道访问的第一多端口多存储体结构和可由第二组多个通道访问的第二多端口多存储体结构。

8. 发明申请

US20110233718A1 Heterogeneous Technology Integration 审中-公开
标题翻译：异构技术集成
公开(公告)号：US20110233718A1
公开(公告)日：2011-09-29
申请号：US12731520
申请日：2010-03-25
申请人： Jonghae Kim , Evgeni P. Gousev , Matthew Michael Nowak
发明人： Jonghae Kim , Evgeni P. Gousev , Matthew Michael Nowak
IPC分类号： H01L23/52 , H01L23/488 , H01L23/48 , H01L21/70 , H01L23/49
CPC分类号： H01L25/0655 , H01L24/73 , H01L24/92 , H01L25/18 , H01L29/0657 , H01L2224/16105 , H01L2224/16137 , H01L2224/16195 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/73207 , H01L2224/73257 , H01L2224/92227 , H01L2924/10155 , H01L2924/10253 , H01L2924/00 , H01L2924/00014
摘要： A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump.
摘要翻译：具有由多种技术制成的至少一层的异质集成电路和制造异质集成电路的方法。异质集成电路包括封装衬底，第一技术的第一裸片和第二技术的第二裸片，其中两个裸片位于同一层。一个模具可以围绕另一个模具。异质集成电路还可以包括耦合两个管芯的引线接合和/或水平微凸块。异质集成电路还可以包括引线接合或将一个管芯耦合到封装衬底的垂直微突起。垂直微凸块耦合可以包括通孔。这两种技术可以是包括CMOS，玻璃，蓝宝石和石英在内的各种技术。一个管芯也可以在同一层上与另一个管芯相邻，并且两个管芯使用水平微型焊盘进行耦合。

9. 发明申请

US20110087846A1 Accessing a Multi-Channel Memory System Having Non-Uniform Page Sizes 有权
标题翻译：访问具有不一致页面大小的多通道内存系统
公开(公告)号：US20110087846A1
公开(公告)日：2011-04-14
申请号：US12576693
申请日：2009-10-09
申请人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
发明人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , Y02D10/14
摘要： A method includes predicting a memory access pattern of each master of a plurality of masters. The plurality of masters can access a multi-channel memory via a crossbar interconnect, where the multi-channel memory has a plurality of banks The method includes identifying a page size associated with each bank of the plurality of banks The method also includes assigning at least one bank of the plurality of banks to each master of the plurality of masters based on the memory access pattern of each master.
摘要翻译：一种方法包括预测多个主机的每个主机的存储器访问模式。多个主器件可以经由跨通道互连访问多通道存储器，其中多通道存储器具有多个存储体。该方法包括识别与多个存储体中的每个存储体相关联的页面大小。该方法还包括至少分配基于每个主机的存储器访问模式，多个存储体中的一个存储体中的多个存储体的每一个存储模块。

10. 发明申请

US20110035529A1 Partitioning a Crossbar Interconnect in a Multi-Channel Memory System 有权
标题翻译：在多通道存储器系统中分隔交叉开关互连
公开(公告)号：US20110035529A1
公开(公告)日：2011-02-10
申请号：US12536991
申请日：2009-08-06
申请人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
发明人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
IPC分类号： G06F13/00
CPC分类号： G06F13/1663 , G06F13/1684 , Y02D10/14
摘要： A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters.
摘要翻译：一种方法包括从多个主器件识别第一组主器件和第二组主器件。多个主机通过交叉开关互连访问多通道存储器。该方法包括将交叉开关互连划分成多个分区，其包括至少对应于第一组主机的第一分区和对应于第二组主机的第二分区。该方法还包括在多通道存储器内分配第一组缓冲区。第一组缓冲区对应于第一组主机。该方法还包括在多通道存储器内分配第二组缓冲区。第二组缓冲器对应于第二组主机。

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