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1. 发明授权

US07079539B2 Method and apparatus for classification of packet data prior to storage in processor buffer memory 失效
公开(公告)号：US07079539B2
公开(公告)日：2006-07-18
申请号：US10029705
申请日：2001-12-21
申请人： Mauricio Calle , Joel R. Davidson , Betty A. McDaniel
发明人： Mauricio Calle , Joel R. Davidson , Betty A. McDaniel
IPC分类号： H04L12/28 , H04L12/50 , H04Q11/00
CPC分类号： H04L49/30 , H04L49/103
摘要： A network processor or other type of processor includes in an illustrative embodiment a first pass classifier coupled to first memory circuitry in the form of a relatively small internal memory, and a second pass classifier coupled to second memory circuitry in the form of a larger internal buffer memory. The first memory circuitry is configurable to store at least a portion of a given packet to be processed by the first pass classifier. The second memory circuitry is configurable to store a different and preferably smaller portion of the given packet to permit processing thereof by the second pass classifier. The portion of the given packet storable in the second memory circuitry is a portion of the given packet determined by a first pass classification, performed by the first pass classifier, to be required for a second pass classification, performed by the second pass classifier. Advantageously, the invention reduces the size of the packet portion required to be stored in the second memory circuitry, thereby reducing the required memory of the processor. The processor may be configured as a network processor integrated circuit to provide an interface between a network from which the packet is received and a switch fabric in a router or switch.

2. 发明授权

US5890006A Apparatus for extracting instruction specific bytes from an instruction 失效
标题翻译：用于从指令中提取指令特定字节的装置
公开(公告)号：US5890006A
公开(公告)日：1999-03-30
申请号：US989794
申请日：1997-12-12
申请人： Thang M. Tran , Mauricio Calle , Shane Southard
发明人： Thang M. Tran , Mauricio Calle , Shane Southard
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/3842
摘要： A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. In one embodiment, to expedite the dispatch of instructions, the first microcode instruction of the cache line is identified during predecode and stored as a microcode pointer. When the cache line is scanned for dispatch, the microcode pointer is used to identify the first microcode instruction which is conveyed to the MROM unit. In another embodiment, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the microcode pointer and the functional bits of the predecode data to multiplex instruction specific bytes of the first microcode instruction to the MROM unit. If the predicted first microcode instruction is not the actual first microcode instruction, then in a subsequent clock cycle, the actual microcode instruction is dispatched the MROM unit and the incorrectly predicted microcode instruction is canceled.
摘要翻译：超标量微处理器预处理指令数据以识别指令的边界和指令的类型。在一个实施例中，为了加快指令的分派，在预解码期间识别高速缓存行的第一微代码指令，并将其存储为微代码指针。当缓存行被扫描以进行调度时，微代码指针用于识别被传送到MROM单元的第一微代码指令。在另一个实施例中，预测第一扫描指令是微代码指令，并且被调度到MROM单元。微代码扫描电路使用微代码指针和预解码数据的功能位将第一微代码指令的指令特定字节复用到MROM单元。如果预测的第一微代码指令不是实际的第一微代码指令，则在随后的时钟周期中，实际的微代码指令被分派到MROM单元，并且错误地预测的微代码指令被取消。

3. 发明授权

US07246102B2 Method of improving the lookup performance of three-type knowledge base searches 有权
标题翻译：提高三类知识库搜索查找性能的方法
公开(公告)号：US07246102B2
公开(公告)日：2007-07-17
申请号：US10037040
申请日：2001-12-21
申请人： Betty A. McDaniel , William Edward Baker , Narender R. Vangati , Mauricio Calle , James T. Kirk
发明人： Betty A. McDaniel , William Edward Baker , Narender R. Vangati , Mauricio Calle , James T. Kirk
IPC分类号： G06F17/00 , G06F7/00 , G06N5/02 , H04L12/28
CPC分类号： G06N5/02 , Y10S706/934 , Y10S707/99942
摘要： A decision tree, representing a knowledge base, is segmented into at least two decision tree portions. The lower portion includes the tree entry point and is stored in a memory element with a faster access time than the upper portion, which includes the terminating element of the decision tree. Thus during the process of reading the tree entries for comparing them with the search object, the search entries in the lower portion of the tree can be read faster than the search entries in the upper portion, resulting in a faster traversal through the entire decision tree.
摘要翻译：代表知识库的决策树被分割成至少两个决策树部分。下部包括树入口点，并且被存储在具有比包括决策树的终止元素的上部更快的访问时间的存储元件中。因此，在读取用于将它们与搜索对象进行比较的树条目的过程中，树的下部的搜索条目可以比上部的搜索条目更快地读取，导致通过整个决策树的更快的遍历。

4. 发明授权

US06944731B2 Dynamic random access memory system with bank conflict avoidance feature 有权
标题翻译：具有银行冲突避免功能的动态随机存取存储系统
公开(公告)号：US06944731B2
公开(公告)日：2005-09-13
申请号：US10025331
申请日：2001-12-19
申请人： Gregg A. Bouchard , Mauricio Calle , Ravi Ramaswami
发明人： Gregg A. Bouchard , Mauricio Calle , Ravi Ramaswami
IPC分类号： G06F12/06 , G06F13/16 , G11C7/00 , G06F12/00
CPC分类号： G06F13/1647 , Y02D10/14
摘要： A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks configured for storing a plurality of data items. More particularly, a given data item is stored as multiple copies of the data item with the multiple copies being stored in respective ones of a designated minimum number of the memory banks. The memory controller is adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence.
摘要翻译：具有多个存储体的存储器系统被配置为防止存取请求之间的存储体冲突。存储器系统包括存储器控制器和可操作地耦合到存储器控制器的多个存储器组，其中每个存储器组被配置用于存储多个数据项。更具体地，给定数据项被存储为数据项的多个副本，其中多个副本被存储在指定的最小数量的存储体的相应的一个中。存储器控制器适于根据指定的存储体访问顺序处理存储在存储体中的数据项的访问请求。

5. 发明申请

US20110193589A1 On-Chip Sensor For Measuring Dynamic Power Supply Noise Of The Semiconductor Chip 有权
标题翻译：用于测量半导体芯片的动态电源噪声的片上传感器
公开(公告)号：US20110193589A1
公开(公告)日：2011-08-11
申请号：US12703233
申请日：2010-02-10
申请人： Lew G. Chua-Eoan , Boris Andreev , Christopher Phan , Amirali Shayan , Xiaohua Kong , Mikhail Popovich , Mauricio Calle , IK-Joon Chang
发明人： Lew G. Chua-Eoan , Boris Andreev , Christopher Phan , Amirali Shayan , Xiaohua Kong , Mikhail Popovich , Mauricio Calle , IK-Joon Chang
IPC分类号： H03K19/00 , G01R19/00
CPC分类号： G01R31/31721 , G01R29/26
摘要： An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.
摘要翻译：片上传感器测量半导体芯片上的动态电源噪声，如电压下降。采用原位逻辑，对芯片功能逻辑电源上存在的噪声敏感。示例性功能逻辑包括芯片的微处理器，加法器和/或其他功能逻辑。原位逻辑执行一些操作，并且执行该操作所需的时间量（即，操作延迟）对电源上存在的噪声敏感。因此，通过评估原位逻辑的操作延迟，可以测量电源上存在的噪声量。

6. 发明授权

US07088719B2 Processor with packet processing order maintenance based on packet flow identifiers 有权
公开(公告)号：US07088719B2
公开(公告)日：2006-08-08
申请号：US10032025
申请日：2001-12-21
申请人： David Allen Brown , Mauricio Calle , Abraham Prasad
发明人： David Allen Brown , Mauricio Calle , Abraham Prasad
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/10 , H04L49/10 , H04L49/254
摘要： A processor having a packet processing order maintenance feature includes classification circuitry operative to identify for each of a plurality of packets received in the processor a corresponding packet flow identifier, control circuitry operatively coupled to the classification circuitry, and at least one operational unit operatively coupled to the control circuitry. The control circuitry is operative to direct one or more packets having a given packet flow identifier to the operational unit(s) in a manner that maintains a desired function call sequencing over the one or more packets having the given packet flow identifier for one or more order-dependent processing tasks in the processor.

7. 发明授权

US06915480B2 Processor with packet data flushing feature 失效
标题翻译：处理器具有分组数据冲洗功能
公开(公告)号：US06915480B2
公开(公告)日：2005-07-05
申请号：US10029704
申请日：2001-12-21
申请人： Mauricio Calle , Joel R. Davidson , James T. Kirk , Betty A. McDaniel , Maurice A. Uebelhor
发明人： Mauricio Calle , Joel R. Davidson , James T. Kirk , Betty A. McDaniel , Maurice A. Uebelhor
IPC分类号： G06F11/00 , H03M13/00 , H04L1/00
CPC分类号： H04L1/201 , H04L1/0061 , H04L1/0082 , H04L2001/0092
摘要： A network processor or other type of processor includes first classification circuitry, scheduling circuitry and second classification circuitry. The first classification circuitry is configured to determine for a given packet received by the processor whether the packet has one or more errors. The scheduling circuitry in an illustrative embodiment receives an indication of the error determination made by the first classification circuitry, and based on the indication controls the dropping of the given packet from the processor memories if the packet has one or more errors, e.g., via a flush transmit command. The second classification circuitry, which may be implemented as a single classification engine or a set of such engines, may be configured to perform at least one classification operation for the given packet, e.g., if the packet is supplied thereto by the scheduling circuitry.
摘要翻译：网络处理器或其他类型的处理器包括第一分类电路，调度电路和第二分类电路。第一分类电路被配置为确定由处理器接收到的给定分组数据包是否具有一个或多个错误。说明性实施例中的调度电路接收由第一分类电路作出的错误确定的指示，并且如果分组具有一个或多个错误，则基于该指示控制来自处理器存储器的给定分组的丢弃，例如，经由 flush发送命令。可以被实现为单个分类引擎或一组这样的引擎的第二分类电路可以被配置为对给定分组执行至少一个分类操作，例如，如果分组被调度电路提供给它。

8. 发明授权

US06839797B2 Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem 有权
标题翻译：多库调度，以提高基于DRAM的随机存取存储器子系统中树访问的性能
公开(公告)号：US06839797B2
公开(公告)日：2005-01-04
申请号：US10026352
申请日：2001-12-21
申请人： Mauricio Calle , Ravi Ramaswami
发明人： Mauricio Calle , Ravi Ramaswami
IPC分类号： G06F12/06 , G06F12/00 , G06F12/02 , G06F12/08 , G06F13/16 , G11C7/00
CPC分类号： G06F13/1647 , Y02D10/14
摘要： A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.
摘要翻译：存储器管理的方法和系统将多组存储器件组合成独立的通道，其中每一组存储器件都包含重复的数据。树存储器控制器控制对每个通道中的每个存储体的数据读取和写入访问。每个渠道中的每个银行的银行排队跟踪银行的可用性。当在树存储器控制器处接收到读或写请求时，控制器检查通道中每个存储体的可用性，识别第一可用存储体，并从第一可用存储体执行读请求。响应于写入请求，控制器一旦确认要写入的数据对于所选择的存储器字长度是完整的则阻止所有读取请求。每个读取请求队列一旦为空，控制器就会同时发起完整数据字的突发模式传输到所有存储库。

9. 发明授权

US06804692B2 Method and apparatus for reassembly of data blocks within a network processor 有权
标题翻译：用于在网络处理器内重新组装数据块的方法和装置
公开(公告)号：US06804692B2
公开(公告)日：2004-10-12
申请号：US10037082
申请日：2001-12-21
申请人： Joel R. Davidson , James T. Kirk , Mauricio Calle
发明人： Joel R. Davidson , James T. Kirk , Mauricio Calle
IPC分类号： G06F700
CPC分类号： H04L69/12
摘要： A method and apparatus for reassembling data blocks back into their constituent data packets in a network processor. Each data block associated with a packet is assigned a unique queue identifier for use in assembling all blocks from the same packet. The packet is also assigned a packet identifier, a start of packet identifier and an end of packet identifier for use by downstream network processors to process the packet. The blocks are assembled according to the assigned queue identifier until the last block of a packet is received, at which time the packet reassembly is complete.
摘要翻译：一种在网络处理器中将数据块重组成其组成数据分组的方法和装置。与分组相关联的每个数据块被分配唯一的队列标识符，用于组合来自相同分组的所有块。分组还被分配了分组标识符，分组标识符的开始和分组标识符的结尾，以供下游网络处理器使用以处理分组。这些块根据分配的队列标识符进行组装，直到接收到分组的最后一个块，此时分组重组完成。

10. 发明授权

US6134650A Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data 失效
标题翻译：用于在扫描预解码数据之前将第一扫描指令预测为微代码指令的装置和方法
公开(公告)号：US6134650A
公开(公告)日：2000-10-17
申请号：US989262
申请日：1997-12-12
申请人： Gerald D. Zuraski, Jr. , Shane Southard , Mauricio Calle
发明人： Gerald D. Zuraski, Jr. , Shane Southard , Mauricio Calle
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/3802
摘要： A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. When the cache line is scanned for dispatch, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the location of the first scanned instruction and the functional bits of the predecode data to multiplex instruction specific bytes of the first scanned instruction to the MROM unit. If the first scanned instruction is not the first microcode instruction, then in a subsequent clock cycle, the first microcode instruction is dispatched the MROM unit and the mispredicted instruction is canceled.
摘要翻译：超标量微处理器预处理指令数据以识别指令的边界和指令的类型。当缓存行被扫描发送时，第一个扫描的指令被预测为微码指令，并被发送到MROM单元。微代码扫描电路使用第一扫描指令的位置和预解码数据的功能位将第一扫描指令的指令特定字节复用到MROM单元。如果第一扫描指令不是第一微代码指令，则在随后的时钟周期中，第一微代码指令被分配到MROM单元，并且取消了误预测指令。

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