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1. 发明授权

US5230058A IC chip having volatile memory cells simultaneously loaded with initialization data from uniquely associated non-volatile memory cells via switching transistors 失效
标题翻译：具有易失性存储单元的IC芯片通过开关晶体管同时加载来自唯一关联的非易失性存储单元的初始化数据
公开(公告)号：US5230058A
公开(公告)日：1993-07-20
申请号：US520777
申请日：1990-05-08
申请人： Niraj Kumar , Mazin Khurshid , John Tran
发明人： Niraj Kumar , Mazin Khurshid , John Tran
IPC分类号： G06F9/445
CPC分类号： G06F9/4403
摘要： Initial data and/or control bits of registers within a digital integrated circuit are simultaneously loaded from localized non-volatile memory cells provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.
摘要翻译：数字集成电路内的寄存器的初始数据和/或控制位由作为电路的一部分提供的局部非易失性存储单元同时加载。这种加载是在每次电路初始化时完成的，例如当电源首次被接通到其中电路是其一部分的系统时。该技术的重要用途是与诸如串行通信控制器的计算机外围电路芯片。

2. 发明授权

US5239237A Control circuit having outputs with differing rise and fall times 失效
标题翻译：具有不同上升和下降时间的输出的控制电路
公开(公告)号：US5239237A
公开(公告)日：1993-08-24
申请号：US958507
申请日：1992-10-08
申请人： John Tran , Mazin Khurshid
发明人： John Tran , Mazin Khurshid
IPC分类号： G11C7/22 , G11C8/18 , H03K5/02 , H03K5/12
CPC分类号： G11C7/22 , G11C8/18 , H03K5/02 , H03K5/12
摘要： A control circuit suitable for generating control signals for controlling the bit and select lines for a static RAM and also for use in a buffer for reducing transient current and for controlling the slew rate. The circuit comprises a pull up and a pull down transistor, each having a first and a second terminal, and a passing gate connecting the second terminals of the two transistors. The gates of the two transistors are controlled by a signal. A first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and the second control signal at a second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal. When the control circuit is used for controlling a static RAM, the passing gate is always turned on. The two control signals are then used to control the bit and select lines of the static RAM. When a control signal is used in a buffer comprising a pull up and a pull down transistor, the input signal to the buffer is applied to the gate of the transistors ind the control circuit. The two control signals are applied to the gates of the pull up and pull down transistors of the buffer to reduce transient current.
摘要翻译：适用于产生用于控制位的控制信号和用于静态RAM的选择线的控制电路，并且还用于缓冲器中以减少瞬态电流并用于控制转换速率。电路包括上拉和下拉晶体管，每个具有第一和第二端子，以及连接两个晶体管的第二端子的通过栅极。两个晶体管的栅极由一个信号控制。上拉晶体管的第二端子处的第一控制信号相对于输入信号具有快速上升时间和缓慢下降时间，并且在下拉晶体管的第二端处的第二控制信号具有快速下降时间和缓慢上升相对于输入信号的时间。当控制电路用于控制静态RAM时，通过门总是打开。然后，两个控制信号用于控制静态RAM的位和选择行。当在包括上拉和下拉晶体管的缓冲器中使用控制信号时，向缓冲器的输入信号施加到控制电路的晶体管的栅极。两个控制信号被施加到缓冲器的上拉和下拉晶体管的栅极以减少瞬态电流。

3. 发明授权

US5187686A Control circuit having outputs with differing rise and fall times 失效
标题翻译：具有不同上升和下降时间的输出的控制电路
公开(公告)号：US5187686A
公开(公告)日：1993-02-16
申请号：US479865
申请日：1990-02-14
申请人： John Tran , Mazin Khurshid
发明人： John Tran , Mazin Khurshid
IPC分类号： G11C7/22 , G11C8/18 , H03K5/02 , H03K5/12
CPC分类号： G11C7/22 , G11C8/18 , H03K5/02 , H03K5/12
摘要： A control circuit suitable for generating control signals for controlling the bit and select lines for a static RAM and also for use in a buffer for reducing transient current and for controlling the slew rate. The circuit comprises a pull up and a pull down transistor, each having a first and a second terminal, and a passing gate connecting the second terminals of the two transistors. The gates of the two transistors are controlled by a signal. A first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and the second control signal at a second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal. When the control circuit is used for controlling a static RAM, the passing gate is always turned on. The two control signals are then used to control the bit and select lines of the static RAM. When a control signal is used in a buffer comprising a pull up and a pull down transistor, the input signal to the buffer is applied to the gate of the transistors in the control circuit. The two control signals are applied to the gates of the pull up and pull down transistors of the buffer to reduce transient current. In a further improvement, where the buffer includes a second inverter including a second pull up and a second pull down transistor, two feedback paths are employed to control the gates of the two transistors in the second inverter to control the slew rate of the buffer. The passing gate of the control circuit may be turned on or off by an enabling circuit so that if the circuit is implemented in an integrated circuit having input and output pins, the control circuit can be tri-stated so that an output pin may be used as an input pin when the passing gate is disabled.
摘要翻译：适用于产生用于控制位的控制信号和用于静态RAM的选择线的控制电路，并且还用于缓冲器中以减少瞬态电流并用于控制转换速率。电路包括上拉和下拉晶体管，每个具有第一和第二端子，以及连接两个晶体管的第二端子的通过栅极。两个晶体管的栅极由一个信号控制。上拉晶体管的第二端子处的第一控制信号相对于输入信号具有快速上升时间和缓慢下降时间，并且在下拉晶体管的第二端处的第二控制信号具有快速下降时间和缓慢上升相对于输入信号的时间。当控制电路用于控制静态RAM时，通过门总是打开。然后，两个控制信号用于控制静态RAM的位和选择行。当在包括上拉和下拉晶体管的缓冲器中使用控制信号时，缓冲器的输入信号被施加到控制电路中的晶体管的栅极。两个控制信号被施加到缓冲器的上拉和下拉晶体管的栅极以减少瞬态电流。在进一步的改进中，其中缓冲器包括具有第二上拉和第二下拉晶体管的第二反相器，采用两个反馈路径来控制第二反相器中的两个晶体管的栅极来控制缓冲器的转换速率。控制电路的通过门可以由使能电路导通或截止，使得如果电路在具有输入和输出引脚的集成电路中实现，则控制电路可以是三态的，使得可以使用输出引脚作为禁止通过门时的输入引脚。

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