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    • 9. 发明申请
    • System and Method of Redundancy in Network Communications
    • 网络通信冗余系统与方法
    • US20140105592A1
    • 2014-04-17
    • US13652156
    • 2012-10-15
    • Deepak KatariaJian-lin MuMichael GreenJohn Brian Pipe
    • Deepak KatariaJian-lin MuMichael GreenJohn Brian Pipe
    • H04B10/08
    • H04B10/032
    • The present disclosure includes a network element comprising a first card configured to receive a duplicatively split first signal comprising a data component and a management component, and further configured to receive and transmit a duplicatively split second signal, and a similar second card. The network element also includes a selector configured to select either the first card or the second card to receive the management component of the first signal and to detect a change in designation between the first card and the second card to transmit the second signal. The selector is also configured to modify the selection to select the card designated to transmit the second signal to also receive the management component of the first signal. The disclosure also includes associated methods and systems.
    • 本公开包括网络元件,其包括被配置为接收包括数据组件和管理组件的重复分割的第一信号的第一卡,并且还被配置为接收和发送重复分割的第二信号和类似的第二卡。 网络元件还包括选择器,其被配置为选择第一卡或第二卡以接收第一信号的管理组件,并且检测第一卡和第二卡之间的指定变化以发送第二信号。 选择器还被配置为修改选择以选择指定为发送第二信号的卡,以接收第一信号的管理组件。 本公开还包括相关联的方法和系统。
    • 10. 发明申请
    • SHADER SERIALIZATION AND INSTANCE UNROLLING
    • SHADER SERIALIZATION和INSTANCE UNROLLING
    • US20140092092A1
    • 2014-04-03
    • US13631866
    • 2012-09-29
    • YUNJIU LIMICHAEL GREEN
    • YUNJIU LIMICHAEL GREEN
    • G06T17/20G06T15/80
    • G06T15/80G06F9/44G06T15/50G06T17/20G06T2200/28G06T2210/52
    • A graphics engine with shader unit thread serializing and instance unrolling functionality that executes multi-threaded shader logic in a single hardware thread is described. Hardware accelerated tessellation functionality is implemented utilizing programmable pipeline stages that allow custom, runtime configuration of graphics hardware utilizing programs compiled from a high level shader language that are executed using one or more shader execution cores. In one embodiment, multiple shader unit program threads are serialized to run in one hardware thread to allow a greater number of instructions to be executed on the shader cores and preserve hardware threads for primitive processing by other shader units.
    • 描述了具有着色器单元线程序列化和在单个硬件线程中执行多线程着色器逻辑的实例展开功能的图形引擎。 使用可编程流水线阶段来实现硬件加速镶嵌功能,这些阶段允许图形硬件的自定义,运行时配置利用使用一个或多个着色器执行核执行的高级着色器语言编译的程序。 在一个实施例中,多个着色器单元程序线程被串行化以在一个硬件线程中运行,以允许在着色器核上执行更多数量的指令,并保留硬件线程以供其他着色器单元进行原始处理。