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    • 7. 发明授权
    • Methods and apparatus for quarter-pel refinement in a SIMD array processor
    • SIMD阵列处理器中四分之一像素细化的方法和装置
    • US08208553B2
    • 2012-06-26
    • US11736849
    • 2007-04-18
    • Mihailo M. StojancicGerald George Pechanek
    • Mihailo M. StojancicGerald George Pechanek
    • H04N7/26
    • H04N19/523H04N19/43H04N19/436
    • An apparatus and a method for quarter-pel motion compensated search are described in the context of an array processor with tightly coupled, multi-cycle hardware assist attached to each node. A quarter-pel motion compensated search (QPMCS) instruction initiates the quarter-pel motion compensated search pipeline operation. An instruction decode and instruction operation control unit generates a starting address for a 4×4 block of a current macro block search operation indicating where to fetch the pel values. An interpolation unit determines at least eight neighboring quarter-pels per pipeline stage based on the 4×4 block of pel values. An absolute value of difference function computes the absolute value of difference values between a current macro block pel and the at least eight neighboring quarter-pels per pipeline stage. An accumulator accumulates at least eight summation values for the 4×4 block at quarter-pel positions per pipeline stage.
    • 在具有连接到每个节点的紧密耦合的多周期硬件辅助的阵列处理器的上下文中描述了用于四分之一像素运动补偿搜索的装置和方法。 四分之一像素运动补偿搜索(QPMCS)指令启动四分之一像素运动补偿搜索管道操作。 指令解码和指令操作控制单元产生指示在哪里获取像素值的当前宏块搜索操作的4×4块的起始地址。 内插单元基于像素值的4×4块来确定每个流水线阶段的至少八个相邻四分之一像素。 差分函数的绝对值计算当前宏块和每个流水线阶段至少八个相邻四分之一像素之间的差值的绝对值。 累加器在每个流水线阶段的四分之一像素位置累积至少八个累加值,用于4×4块。