专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09729157B2 Variable clock phase generation method and system 有权
公开(公告)号：US09729157B2
公开(公告)日：2017-08-08
申请号：US14622706
申请日：2015-02-13
申请人： Mindspeed Technologies, Inc.
发明人： Wim F. Cops
IPC分类号： H03L7/06 , H03L7/081 , H03K5/06
CPC分类号： H03L7/0814 , H03K5/06 , H03L7/0816
摘要： A variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.

2. 发明授权

US08934598B2 Integrated video equalizer and jitter cleaner 有权
标题翻译：集成视频均衡器和抖动清除器
公开(公告)号：US08934598B2
公开(公告)日：2015-01-13
申请号：US13857876
申请日：2013-04-05
申请人： Mindspeed Technologies, Inc.
发明人： Atul Krishna Gupta , Ryan Suresh Latchman , Nicolas Alain Paul Nodenot
IPC分类号： H04L7/00 , H04N5/21 , H04L25/03
CPC分类号： H04N5/21 , H04L25/03 , H04L25/03146 , H04L25/03885
摘要： An integrated system for adaptive equalization and jitter reduction of a video signal that includes an adaptive equalizer and a jitter cleaner located on one integrated circuit within a single package. An adaptive equalizer applies frequency specific signal modification to the received signal. A bit rate detector determines a bit rate of the video signal or the equalized signal. The jitter cleaner couples to the adaptive equalizer output and processes the equalized signal to reduce jitter in the equalized signal. A multiplexer receives the equalized signal and the jitter cleaner output and, responsive to a control signal, outputs either the equalized signal or the jitter cleaner output signal. A status monitor may optionally be included to compare the detected bit rate to a bit rate threshold, and a responsive to the comparing activate or deactivate the jitter cleaner and output either the equalized signal or jitter cleaner output.
摘要翻译：一种用于视频信号的自适应均衡和抖动降低的集成系统，其包括位于单个封装内的一个集成电路上的自适应均衡器和抖动清除器。自适应均衡器对接收到的信号应用频率特定信号修改。比特率检测器确定视频信号或均衡信号的比特率。抖动清除器耦合到自适应均衡器输出并处理均衡信号以减少均衡信号中的抖动。复用器接收均衡信号和抖动清除器输出，并且响应于控制信号输出均衡信号或抖动清除器输出信号。可以可选地包括状态监视器以将检测到的比特率与比特率阈值进行比较，并且响应于比较激活或去激活抖动清除器并输出均衡信号或抖动清除器输出。

3. 发明申请

US20140021597A1 High Speed Signal Conditioning Package 有权
标题翻译：高速信号调理包
公开(公告)号：US20140021597A1
公开(公告)日：2014-01-23
申请号：US13940121
申请日：2013-07-11
申请人： Mindspeed Technologies, Inc.
发明人： Atul K. Gupta , Ryan S. Latchman , Marek S. Tlalka
IPC分类号： H01L23/488
CPC分类号： H01L23/488 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/05553 , H01L2224/05554 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2924/00014 , H01L2924/15747 , H05K1/0209 , H05K1/111 , H05K1/141 , H05K2201/041 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A package and integrated circuit assembly is configured to perform signal conditioning on a signal. The assembly includes a line card having line card contacts that correspond to conductors in the line card connector. Two or more integrated circuits are configured to perform signal conditioning on the signal and the two or more integrated circuits are configured within a package into at least a first row and a second row on the package. The package includes a grid array of bonding pads to electrically connect to the two or more integrated circuits through bond wires or down bonds such that the structure of the grid array corresponds in physical arrangement or bond pad pitch to the line card contacts. This assembly also includes an electrical connection from the two or more integrated circuits to the line card through the package.
摘要翻译：封装和集成电路组件被配置为对信号执行信号调节。组件包括具有对应于线卡连接器中的导体的线卡触点的线卡。两个或多个集成电路被配置为对信号执行信号调节，并且两个或更多个集成电路在封装内配置成封装中的至少第一行和第二行。封装包括焊盘的栅格阵列，以通过接合线或向下接合电连接到两个或多个集成电路，使得栅格阵列的结构在物理布置或接合焊盘间距对应于线卡接触。该组件还包括通过封装从两个或多个集成电路到线卡的电连接。

4. 发明申请

US20160191196A1 DC-COUPLED LASER DRIVER WITH AC-COUPLED TERMINATION ELEMENT 审中-公开
标题翻译：直流耦合激光驱动器与交流耦合终端元件
公开(公告)号：US20160191196A1
公开(公告)日：2016-06-30
申请号：US14588267
申请日：2014-12-31
申请人： MINDSPEED TECHNOLOGIES, INC.
发明人： Matteo Troiani , Cristiano Bazzani , Will Will Wang , Kevin McDonald , Atul Gupta
IPC分类号： H04J14/08 , H04Q11/00
CPC分类号： H04Q11/0066 , H01S5/0428 , H04B10/502 , H04B10/504 , H04Q2011/0033 , H04Q2011/0035 , H04Q2011/0086
摘要： An optical signal module including a driver and an optical signal module. The driver includes a differential pair configured to receive and process an input signal to create a drive signal. A modulation current source provides a modulation current to the differential pair. One or more termination resistors connected to the differential pair for impedance matching. A first switch, responsive to a first control signal, maintains charge on a charge storage device. The optical signal module includes an optical signal generator arranged between a supply voltage node and a bias current node. The optical signal generator receives the drive signal and generates an optical signal representing the input signal. A second switch is between a supply voltage node the bias current node. The second switch, responsive to second control signal, selectively establishes a short between the supply voltage node the bias current node.
摘要翻译：包括驱动器和光信号模块的光信号模块。驱动器包括配置为接收和处理输入信号以产生驱动信号的差分对。调制电流源向差分对提供调制电流。连接到差分对的一个或多个终端电阻用于阻抗匹配。响应于第一控制信号的第一开关在电荷存储装置上维持电荷。光信号模块包括布置在电源电压节点和偏置电流节点之间的光信号发生器。光信号发生器接收驱动信号并产生表示输入信号的光信号。第二个开关是电源节点之间的偏置电流节点。响应于第二控制信号的第二开关选择性地在电源电压节点之间建立偏置电流节点之间的短路。

5. 发明授权

US09245828B2 High speed signal conditioning package 有权
标题翻译：高速信号调理包装
公开(公告)号：US09245828B2
公开(公告)日：2016-01-26
申请号：US13940121
申请日：2013-07-11
申请人： Mindspeed Technologies, Inc.
发明人： Atul K. Gupta , Ryan S. Latchman , Marek S. Tlalka
IPC分类号： H01L23/488 , H01L23/00 , H01L25/065 , H05K1/02 , H05K1/11 , H05K1/14
CPC分类号： H01L23/488 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/05553 , H01L2224/05554 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2924/00014 , H01L2924/15747 , H05K1/0209 , H05K1/111 , H05K1/141 , H05K2201/041 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A package and integrated circuit assembly is configured to perform signal conditioning on a signal. The assembly includes a line card having line card contacts that correspond to conductors in the line card connector. Two or more integrated circuits are configured to perform signal conditioning on the signal and the two or more integrated circuits are configured within a package into at least a first row and a second row on the package. The package includes a grid array of bonding pads to electrically connect to the two or more integrated circuits through bond wires or down bonds such that the structure of the grid array corresponds in physical arrangement or bond pad pitch to the line card contacts. This assembly also includes an electrical connection from the two or more integrated circuits to the line card through the package.
摘要翻译：封装和集成电路组件被配置为对信号执行信号调节。组件包括具有对应于线卡连接器中的导体的线卡触点的线卡。两个或多个集成电路被配置为对信号执行信号调节，并且两个或更多个集成电路在封装内配置成封装中的至少第一行和第二行。封装包括焊盘的栅格阵列，以通过接合线或向下接合电连接到两个或多个集成电路，使得栅格阵列的结构在物理布置或接合焊盘间距对应于线卡接触。该组件还包括通过封装从两个或多个集成电路到线卡的电连接。

6. 发明申请

US20150288085A1 EDGE MOUNT CONNECTOR ARRANGEMENT WITH IMPROVED CHARACTERISTIC IMPEDANCE 有权
标题翻译：边缘安装连接器安装具有改进的特性阻抗
公开(公告)号：US20150288085A1
公开(公告)日：2015-10-08
申请号：US14679892
申请日：2015-04-06
申请人： Mindspeed Technologies, Inc.
发明人： Alfredo Moncayo , Brian Hostetter , Luis F. Armenta
IPC分类号： H01R12/57 , H05K1/02 , H05K1/11
CPC分类号： H05K1/025 , H01R24/50 , H05K1/0221 , H05K1/115 , H05K1/117 , H05K2201/0195 , H05K2201/10015 , H05K2201/10189 , H05K2201/10356 , H05K2201/10446
摘要： An electrical interface on a circuit board is disclosed for electrically connecting the circuit board to a connector to reduce reflections and impedance mismatch and increase power transfer from the connector to the signal path of the circuit board. The signal interface includes a signal conductor including a signal pad configured to connect to a connector pin and a waveguide section extending from the signal pad. The waveguide narrows from a signal pad width to connect to a microstrip conductor. A first ground section is spaced rightward from the signal conductor such that the inner edge of the first ground section, angles in correspondence with the narrowing of the waveguide to generally track an outer right edge of the waveguide. A second ground section is spaced leftward from the signal conductor and configured generally similarly to the first ground section.
摘要翻译：公开了电路板上的电接口，用于将电路板电连接到连接器以减少反射和阻抗失配，并增加从连接器到电路板的信号路径的功率传递。信号接口包括信号导体，该信号导体包括被配置为连接到连接器引脚的信号焊盘和从信号焊盘延伸的波导部分。波导从信号焊盘宽度变窄以连接到微带导体。第一接地部分从信号导体向右间隔开，使得第一接地部分的内边缘与波导的变窄相对应，以大致跟踪波导的外右边缘。第二接地部分与信号导体向左隔开，并且大致与第一接地部分类似地配置。

7. 发明申请

US20130329130A1 INTEGRATED VIDEO EQUALIZER AND JITTER CLEANER 有权
标题翻译：集成视频均衡器和抖动清洁器
公开(公告)号：US20130329130A1
公开(公告)日：2013-12-12
申请号：US13857876
申请日：2013-04-05
申请人： Mindspeed Technologies, Inc.
发明人： Atul Krishna Gupta , Ryan Suresh Latchman , Nicolas Alain Paul Nodenot
IPC分类号： H04N5/21
CPC分类号： H04N5/21 , H04L25/03 , H04L25/03146 , H04L25/03885
摘要： An integrated system for adaptive equalization and jitter reduction of a video signal that includes an adaptive equalizer and a jitter cleaner located on one integrated circuit within a single package. An adaptive equalizer applies frequency specific signal modification to the received signal. A bit rate detector determines a bit rate of the video signal or the equalized signal. The jitter cleaner couples to the adaptive equalizer output and processes the equalized signal to reduce jitter in the equalized signal. A multiplexer receives the equalized signal and the jitter cleaner output and, responsive to a control signal, outputs either the equalized signal or the jitter cleaner output signal. A status monitor may optionally be included to compare the detected bit rate to a bit rate threshold, and a responsive to the comparing activate or deactivate the jitter cleaner and output either the equalized signal or jitter cleaner output.
摘要翻译：一种用于视频信号的自适应均衡和抖动降低的集成系统，其包括位于单个封装内的一个集成电路上的自适应均衡器和抖动清除器。自适应均衡器对接收到的信号应用频率特定信号修改。比特率检测器确定视频信号或均衡信号的比特率。抖动清除器耦合到自适应均衡器输出并处理均衡信号以减少均衡信号中的抖动。复用器接收均衡信号和抖动清除器输出，并且响应于控制信号输出均衡信号或抖动清除器输出信号。可以可选地包括状态监视器以将检测到的比特率与比特率阈值进行比较，并且响应于比较激活或去激活抖动清除器并输出均衡信号或抖动清除器输出。

8. 发明申请

US20040181399A1 Signal decomposition of voiced speech for CELP speech coding 有权
标题翻译：用于CELP语音编码的有声语音的信号分解
公开(公告)号：US20040181399A1
公开(公告)日：2004-09-16
申请号：US10799533
申请日：2004-03-11
申请人： Mindspeed Technologies, Inc.
发明人： Yang Gao
IPC分类号： G10L011/06
CPC分类号： G10L19/265 , G10L19/005 , G10L19/087 , G10L19/09 , G10L19/12 , G10L19/20 , G10L21/0208 , G10L21/0232 , G10L21/038 , G10L25/90
摘要： An approach for improving quality of synthesized speech is presented. The input speech or residual is first separated into a voiced portion and a noise portion. The voice portion is coded using CELP methods. The noise portion of the input speech may be estimated at the decoder since it contains minimal voiced speech components. The separation is frequency dependent and is adaptive to the input speech. The separation may be accomplished using a lowpass/highpass filter combination. The information regarding bandwidth of the lowpass/highpass is presented to the decoder to facilitate reproduction of the noise portion of the speech.
摘要翻译：提出了一种提高合成语音质量的方法。输入语音或残差首先分为有声部分和噪声部分。语音部分使用CELP方法进行编码。可以在解码器处估计输入语音的噪声部分，因为它包含最小的有声语音分量。分离是频率依赖的，并且适应于输入语音。可以使用低通/高通滤波器组合来实现分离。关于低通/高通带宽的信息被提供给解码器以便于语音的噪声部分的再现。

9. 发明申请

US20160104500A1 Adaptive Codebook Gain Control for Speech Coding 有权
标题翻译：自适应码本语音编码增益控制
公开(公告)号：US20160104500A1
公开(公告)日：2016-04-14
申请号：US14873610
申请日：2015-10-02
申请人： Mindspeed Technologies, Inc.
发明人： Yang Gao
IPC分类号： G10L19/12 , G10L19/09 , G10L25/90 , G10L19/02
CPC分类号： G10L19/12 , G10L19/0204 , G10L19/09 , G10L19/18 , G10L19/20 , G10L25/90 , G10L2019/0002 , G10L2019/0016
摘要： In accordance with one aspect of the invention, a selector supports the selection of a first encoding scheme or the second encoding scheme based upon the detection or absence of the triggering characteristic in the interval of the input speech signal. The first encoding scheme has a pitch pre-processing procedure for processing the input speech signal to form a revised speech signal biased toward an ideal voiced and stationary characteristic. The pre-processing procedure allows the encoder to fully capture the benefits of a bandwidth-efficient, long-term predictive procedure for a greater amount of speech components of an input speech signal than would otherwise be possible. In accordance with another aspect of the invention, the second encoding scheme entails a long-term prediction mode for encoding the pitch on a sub-frame by sub-frame basis. The long-term prediction mode is tailored to where the generally periodic component of the speech is generally not stationary or less than completely periodic and requires greater frequency of updates from the adaptive codebook to achieve a desired perceptual quality of the reproduced speech under a long-term predictive procedure.
摘要翻译：根据本发明的一个方面，选择器基于输入语音信号的间隔中的触发特性的检测或不存在，支持选择第一编码方案或第二编码方案。第一编码方案具有用于处理输入语音信号以形成偏向理想有声和静态特征的修正语音信号的音调预处理过程。预处理过程允许编码器完全捕获带宽有效的长期预测程序的优点，用于输入语音信号的大量语音分量比否则可能的更多。根据本发明的另一方面，第二编码方案需要一种长期预测模式，用于以子帧为基础对子帧上的音调进行编码。长期预测模式被定制为语音的大致周期性分量通常不是静止的或小于完全周期性的，并且需要来自自适应码本的更高频率的更新以在长时间内实现再现语音的期望感知质量，术语预测程序。

10. 发明申请

US20040190499A1 Method and system for configuring gateways to facilitate a modem connection over a packet network 审中-公开
标题翻译：用于配置网关以促进分组网络上的调制解调器连接的方法和系统
公开(公告)号：US20040190499A1
公开(公告)日：2004-09-30
申请号：US10631947
申请日：2003-07-30
申请人： Mindspeed Technologies, Inc.
发明人： Zhihui Chen , Keith Chu
IPC分类号： H04L012/66
CPC分类号： H04L5/1438 , H04L12/4633 , H04L29/06 , H04L69/08
摘要： There is provided system, device and method for use by a first gateway device to enable communication between a first modem and a second modem, the first gateway device being capable of communicating with the first modem over a first communication line, the first gateway device being capable of communicating with a second gateway device over a packet network, the second gateway device being capable of communicating with the second modem over a second communication line. An example method comprises receiving a call request for the first modem from the second gateway device, placing a call to the first modem, detecting an answer tone transmitted from the first modem over the first communication line in response to the call, detecting a phase reversal in the answer tone, and transmitting a message indicative of the phase reversal to the second gateway device over the packet network.
摘要翻译：提供了由第一网关设备使用以实现第一调制解调器和第二调制解调器之间的通信的系统，设备和方法，第一网关设备能够通过第一通信线路与第一调制解调器通信，第一网关设备为能够通过分组网络与第二网关设备通信，第二网关设备能够通过第二通信线路与第二调制解调器通信。一种示例性方法包括从第二网关设备接收针对第一调制解调器的呼叫请求，向第一调制解调器发出呼叫，响应于该呼叫检测在第一通信线路上从第一调制解调器发送的应答音频，检测相位反转并且通过分组网络向第二网关设备发送指示相位反转的消息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式