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    • 2. 发明授权
    • Speeding up timing analysis by reusing delays computed for isomorphic subcircuits
    • 通过重新使用同构子电路计算的延迟来加快时序分析
    • US07451412B2
    • 2008-11-11
    • US11198451
    • 2005-08-04
    • Larry G. JonesFeng LiMohan Rangan GovindarajBradley R. RoetcisoenderMichael G. Weaver
    • Larry G. JonesFeng LiMohan Rangan GovindarajBradley R. RoetcisoenderMichael G. Weaver
    • G06F17/50
    • G06F17/5031
    • One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist. The system then subdivides the circuit block into a set of subcircuits. The subcircuits are then partitioned into equivalence classes, which contain subcircuits which are topologically isomorphic to each other. Next, the system performs a timing analysis by tracing paths through a timing graph for the circuit block. During this timing analysis, whenever a delay is required for a subcircuit, the system determines if a corresponding delay has been already computed for the equivalence class associated with the subcircuit. If so, the system reuses the delay. If not, the system computes the delay for the subcircuit, and then associates the computed delay with the equivalence class so that the computed delay can be reused for isomorphic subcircuits.
    • 本发明的一个实施例提供了一种系统,其通过重新利用为同构子电路计算的延迟来加速时序分析。 在操作期间,系统接收要分析的电路块,其中电路块是网表的形式。 然后,系统将电路块细分成一组子电路。 然后将子电路分成等价类,其中包含彼此拓扑上同构的子电路。 接下来,系统通过用于电路块的时序图跟踪路径来执行定时分析。 在此定时分析期间,每当子电路需要延迟时,系统确定是否已经为与子电路相关联的等效类计算了相应的延迟。 如果是这样,系统重新使用延迟。 如果不是,则系统计算子电路的延迟,然后将计算的延迟与等价类相关联,使得计算的延迟可以重用于同构子电路。