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1. 发明授权

US08538205B2 Multi-function summing machine 有权
标题翻译：多功能求和机
公开(公告)号：US08538205B2
公开(公告)日：2013-09-17
申请号：US12779976
申请日：2010-05-14
申请人： Emmanuel Sixsou , Mois Navon
发明人： Emmanuel Sixsou , Mois Navon
IPC分类号： G06K9/60 , G06K9/00 , G06K9/40
CPC分类号： G06T1/20
摘要： A system for processing an image including multiple pixels and intensity data thereof. An image memory is adapted for storing the image. An arithmetic core is connectible to the image memory and adapted for inputting the intensity data. The arithmetic core includes a multiple function processing units. One or more of the function processing units includes (i) a processing core adapted for computation of a function of the intensity data and for producing results of the computation, (ii) a first and (iii) a second accumulator for summing the results; and storage adapted to store the results. The function processing units are configured to compute the functions in parallel and sum the results simultaneously for each of the pixels in a single clock cycle.
摘要翻译：一种用于处理包括多个像素的图像和其强度数据的系统。图像存储器适于存储图像。算术核心可连接到图像存储器并且适于输入强度数据。算术核心包括多功能处理单元。一个或多个功能处理单元包括（i）适于计算强度数据的功能并用于产生计算结果的处理核心，（ii）用于求和结果的第一和第三累加器; 以及适于存储结果的存储。功能处理单元被配置为并行地计算功能并且在单个时钟周期中对于每个像素同时求和结果。

2. 发明申请

US20090300629A1 Scheduling of Multiple Tasks in a System Including Multiple Computing Elements 审中-公开
标题翻译：在包含多个计算元素的系统中调度多个任务
公开(公告)号：US20090300629A1
公开(公告)日：2009-12-03
申请号：US12131173
申请日：2008-06-02
申请人： Mois Navon , Elchanan Rushinek , Emmanuel Sixou , Arkady Pann , Yossi Kreinin
发明人： Mois Navon , Elchanan Rushinek , Emmanuel Sixou , Arkady Pann , Yossi Kreinin
IPC分类号： G06F9/44
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A method for controlling parallel process flow in a system including a central processing unit (CPU) attached to and accessing system memory, and multiple computing elements. The computing elements (CEs) each include a computational core, local memory and a local direct memory access (DMA) unit. The CPU stores in the system memory multiple task queues in a one-to-one correspondence with the computing elements. Each task queue, which includes multiple task descriptors, specifies a sequence of tasks for execution by the corresponding computing element. Upon programming the computing element with task queue information of the task queue, the task descriptors of the task queue in system memory are accessed. The task descriptors of the task queue are stored in the local memory of the computing element. The accessing and the storing of the data by the CEs is performed using the local DMA unit. When the tasks of the task queue are executed by the computing element, the execution is typically performed in parallel by at least two of the computing elements. The CPU is interrupted respectively by the computing elements only upon their fully executing the tasks of their respective task queues.
摘要翻译：一种用于控制包括附接到系统存储器和访问系统存储器的中央处理单元（CPU）的系统中的并行处理流程的方法，以及多个计算元件。计算元件（CE）各自包括计算核心，本地存储器和本地直接存储器访问（DMA）单元。 CPU与计算元件一一对应地存储系统存储器中的多个任务队列。包括多个任务描述符的每个任务队列指定了由相应的计算元件执行的任务序列。在使用任务队列的任务队列信息对计算单元进行编程时，访问系统存储器中任务队列的任务描述符。任务队列的任务描述符存储在计算元素的本地存储器中。使用本地DMA单元执行由CE访问和存储数据。当任务队列的任务由计算元件执行时，执行通常由至少两个计算元件并行执行。 CPU只有在完全执行其各自的任务队列的任务时才被计算元件分别中断。

3. 发明申请

US20110307684A1 Image Processing Address Generator 有权
标题翻译：图像处理地址生成器
公开(公告)号：US20110307684A1
公开(公告)日：2011-12-15
申请号：US12797689
申请日：2010-06-10
申请人： Yosef Kreinin , Gil Dogon , Emmanuel Sixsou , Yosi Arbeli , Mois Navon , Roman Sajman
发明人： Yosef Kreinin , Gil Dogon , Emmanuel Sixsou , Yosi Arbeli , Mois Navon , Roman Sajman
IPC分类号： G06K9/54 , G06F9/38 , G06F9/02 , G06F15/76
CPC分类号： G06F9/3853 , G06F9/30043 , G06F9/3555 , G06F9/3889 , G06K9/00791 , G06K9/00986 , G06T1/20
摘要： An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor includes an address generator operatively attached to the memory to access the memory. The address generator is adapted for calculating addresses of the memory over the multiple image frames. The addresses may be calculated over the image frames based upon an image parameter. The image parameter may specify which of the image frames are processed simultaneously. A scalar processor may be attached to the vector processor. The scalar processor provides the image parameter(s) to the address generator for address calculation over the multiple image frames. An input register may be attached to the vector processor. The input register may be adapted to receive a very long instruction word (VLIW) instruction. The VLIW instruction may be configured to transfer only: (i) parameters for image processing calculations over the image frames by the ALU units and (ii) a single bit to the address generator.
摘要翻译：一种图像处理系统，包括矢量处理器和适于附接到矢量处理器的存储器。存储器适于存储多个图像帧。矢量处理器包括可操作地附接到存储器以访问存储器的地址发生器。地址发生器适于计算多个图像帧上的存储器的地址。可以基于图像参数在图像帧上计算地址。图像参数可以指定哪个图像帧被同时处理。标量处理器可以附接到向量处理器。标量处理器将图像参数提供给地址生成器，用于在多个图像帧上进行地址计算。输入寄存器可以附加到向量处理器。输入寄存器可以适于接收非常长的指令字（VLIW）指令。 VLIW指令可以被配置为仅传输：（i）由ALU单元在图像帧上进行图像处理计算的参数，以及（ii）到地址生成器的单个位。

4. 发明申请

US20110280495A1 Multi-Function Summing Machine 有权
标题翻译：多功能求和机
公开(公告)号：US20110280495A1
公开(公告)日：2011-11-17
申请号：US12779976
申请日：2010-05-14
申请人： Emmanuel Sixsou , Mois Navon
发明人： Emmanuel Sixsou , Mois Navon
IPC分类号： G06K9/36 , G06F7/50
CPC分类号： G06T1/20
摘要： A system for processing an image including multiple pixels and intensity data thereof. An image memory is adapted for storing the image. An arithmetic core is connectible to the image memory and adapted for inputting the intensity data. The arithmetic core includes a multiple function processing units. One or more of the function processing units includes (i) a processing core adapted for computation of a function of the intensity data and for producing results of the computation, (ii) a first and (iii) a second accumulator for summing the results; and storage adapted to store the results. The function processing units are configured to compute the functions in parallel and sum the results simultaneously for each of the pixels in a single clock cycle.
摘要翻译：一种用于处理包括多个像素的图像和其强度数据的系统。图像存储器适于存储图像。算术核心可连接到图像存储器并且适于输入强度数据。算术核心包括多功能处理单元。一个或多个功能处理单元包括（i）适于计算强度数据的功能并用于产生计算结果的处理核心，（ii）用于求和结果的第一和第二累加器; 以及适于存储结果的存储。功能处理单元被配置为并行计算功能并且在单个时钟周期中对于每个像素同时求和结果。

5. 发明申请

US20110219217A1 System on Chip Breakpoint Methodology 有权
标题翻译：系统片上断点方法论
公开(公告)号：US20110219217A1
公开(公告)日：2011-09-08
申请号：US12779422
申请日：2010-05-13
申请人： Emmanuel Sixsou , Elchanan Rushinek , Mois Navon
发明人： Emmanuel Sixsou , Elchanan Rushinek , Mois Navon
IPC分类号： G06F9/30
CPC分类号： G06F11/362
摘要： A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured to program the computing elements with task descriptors and the computing elements are configured to receive the task descriptors and to perform a computation based on the task descriptors. The task descriptors include a field which specifies a breakpoint state of the computing element. A system level event status register (ESR) attaches to and is accessible by the CPU and the computing elements. Each of the computing elements has a comparator configured to compare the present state of the computing element to the breakpoint state. The computing element is configured to drive a breakpoint event to the event status register (ESR) if the present state of the computing element is the breakpoint state. Each of the computing elements has a halt logic unit operatively attached thereto, wherein the halt logic unit is configured to halt operation of the computing element. The ESR is configurable to drive a breakpoint event to the halt logic units to halt at least one of the computing elements other than the computing element driving the breakpoint event.
摘要翻译：具有调试方法的片上系统（SoC）。片上系统（SoC）包括中央处理单元（CPU）和连接到CPU的多个计算元件。 CPU被配置为使用任务描述符对计算元件进行编程，并且计算元件被配置为接收任务描述符并且基于任务描述符执行计算。任务描述符包括指定计算元素的断点状态的字段。系统级事件状态寄存器（ESR）连接到CPU并可由计算元件访问。每个计算元件具有比较器，其被配置为将计算元件的当前状态与断点状态进行比较。如果计算元件的当前状态是断点状态，则计算元件被配置为将事件状态寄存器（ESR）的断点事件驱动。每个计算元件具有可操作地附接到其上的停止逻辑单元，其中停止逻辑单元被配置为停止计算元件的操作。 ESR可配置为将驱动断点事件的计算元件之外的计算元件中的至少一个停止至停止逻辑单元的断点事件。

6. 发明授权

US08892853B2 Hardware to support looping code in an image processing system 有权
标题翻译：硬件支持图像处理系统中的循环码
公开(公告)号：US08892853B2
公开(公告)日：2014-11-18
申请号：US12797689
申请日：2010-06-10
申请人： Yosef Kreinin , Gil Dogon , Emmanuel Sixsou , Yosi Arbeli , Mois Navon , Roman Sajman
发明人： Yosef Kreinin , Gil Dogon , Emmanuel Sixsou , Yosi Arbeli , Mois Navon , Roman Sajman
IPC分类号： G06F9/34 , G06F9/38 , G06K9/00 , G06F9/355 , G06T1/20 , G06F9/30
CPC分类号： G06F9/3853 , G06F9/30043 , G06F9/3555 , G06F9/3889 , G06K9/00791 , G06K9/00986 , G06T1/20
摘要： An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor includes an address generator operatively attached to the memory to access the memory. The address generator is adapted for calculating addresses of the memory over the multiple image frames. The addresses may be calculated over the image frames based upon an image parameter. The image parameter may specify which of the image frames are processed simultaneously. A scalar processor may be attached to the vector processor. The scalar processor provides the image parameter(s) to the address generator for address calculation over the multiple image frames. An input register may be attached to the vector processor. The input register may be adapted to receive a very long instruction word (VLIW) instruction. The VLIW instruction may be configured to transfer only: (i) parameters for image processing calculations over the image frames by the ALU units and (ii) a single bit to the address generator.
摘要翻译：一种图像处理系统，包括矢量处理器和适于附接到矢量处理器的存储器。存储器适于存储多个图像帧。矢量处理器包括可操作地附接到存储器以访问存储器的地址发生器。地址发生器适于计算多个图像帧上的存储器的地址。可以基于图像参数在图像帧上计算地址。图像参数可以指定哪个图像帧被同时处理。标量处理器可以附接到向量处理器。标量处理器将图像参数提供给地址生成器，用于在多个图像帧上进行地址计算。输入寄存器可以附加到向量处理器。输入寄存器可以适于接收非常长的指令字（VLIW）指令。 VLIW指令可以被配置为仅传输：（i）由ALU单元在图像帧上进行图像处理计算的参数，以及（ii）到地址生成器的单个位。

7. 发明授权

US08656221B2 System on chip breakpoint methodology 有权
标题翻译：系统断点断点方法
公开(公告)号：US08656221B2
公开(公告)日：2014-02-18
申请号：US12779422
申请日：2010-05-13
申请人： Emmanuel Sixsou , Elchanan Rushinek , Mois Navon
发明人： Emmanuel Sixsou , Elchanan Rushinek , Mois Navon
IPC分类号： G06F11/00
CPC分类号： G06F11/362
摘要： A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured to program the computing elements with task descriptors and the computing elements are configured to receive the task descriptors and to perform a computation based on the task descriptors. The task descriptors include a field which specifies a breakpoint state of the computing element. A system level event status register (ESR) attaches to and is accessible by the CPU and the computing elements. Each of the computing elements has a comparator configured to compare the present state of the computing element to the breakpoint state. The computing element is configured to drive a breakpoint event to the event status register (ESR) if the present state of the computing element is the breakpoint state. Each of the computing elements has a halt logic unit operatively attached thereto, wherein the halt logic unit is configured to halt operation of the computing element. The ESR is configurable to drive a breakpoint event to the halt logic units to halt at least one of the computing elements other than the computing element driving the breakpoint event.
摘要翻译：具有调试方法的片上系统（SoC）。片上系统（SoC）包括中央处理单元（CPU）和连接到CPU的多个计算元件。 CPU被配置为使用任务描述符对计算元件进行编程，并且计算元件被配置为接收任务描述符并且基于任务描述符执行计算。任务描述符包括指定计算元素的断点状态的字段。系统级事件状态寄存器（ESR）连接到CPU并可由计算元件访问。每个计算元件具有比较器，其被配置为将计算元件的当前状态与断点状态进行比较。如果计算元件的当前状态是断点状态，则计算元件被配置为将事件状态寄存器（ESR）的断点事件驱动。每个计算元件具有可操作地附接到其上的停止逻辑单元，其中停止逻辑单元被配置为停止计算元件的操作。 ESR可配置为将驱动断点事件的计算元件之外的计算元件中的至少一个停止至停止逻辑单元的断点事件。

8. 发明申请

US20100125717A1 Synchronization Controller For Multiple Multi-Threaded Processors 审中-公开
标题翻译：多个多线程处理器的同步控制器
公开(公告)号：US20100125717A1
公开(公告)日：2010-05-20
申请号：US12272290
申请日：2008-11-17
申请人： Mois Navon
发明人： Mois Navon
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/3851 , G06F9/3824
摘要： A gated-storage system including multiple control interfaces, each control interface operatively connected externally to respective multithreaded processors. The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit and shared between the multithreaded processors. The thread contexts request access to the memory by communicating multiple access requests over the control interfaces. The access requests are from any of the thread contexts within any of the multithreaded processors. A single request storage is shared by the multithreaded processors. A controller stores the access requests in the single request storage within a single clock cycle.
摘要翻译：一种门控存储系统，包括多个控制接口，每个控制接口在外部可操作地连接到相应的多线程处理器。多线程处理器各自具有运行活动线程的线程上下文，以便多线程处理器上运行多个线程上下文。存储器连接到系统级线程通信单元，并在多线程处理器之间共享。线程上下文通过在控制接口上传递多个访问请求来请求访问存储器。访问请求来自任何多线程处理器中的任何线程上下文。单个请求存储由多线程处理器共享。控制器在单个时钟周期内将访问请求存储在单个请求存储中。

9. 发明授权

US07995067B2 Cyclical image buffer 有权
标题翻译：循环图像缓冲区
公开(公告)号：US07995067B2
公开(公告)日：2011-08-09
申请号：US11692941
申请日：2007-03-29
申请人： Mois Navon
发明人： Mois Navon
IPC分类号： G09G5/39 , G09G3/36 , G09G3/20 , G06F13/00
CPC分类号： G06T7/593 , G06T2200/28 , G06T2207/10012 , H04N13/10
摘要： A storage buffer attached to an image processor for stereo image processing. The processor compares a first image and a second image. The storage buffer stores image data of the second image. The storage buffer includes: a data-shifting-hardware mechanism which while the processor compares a patch of the first image to a swath of the second image, the data shifting mechanism using hardware within the storage buffer shifts at least a portion of the swath within the storage buffer. The data-shifting hardware mechanism includes preferably digital multiplexers with respective selectable inputs from adjacent and non-adjacent columns of data within the storage buffer and selectable inputs from adjacent rows of data within the storage buffer.
摘要翻译：连接到图像处理器以用于立体图像处理的存储缓冲器。处理器比较第一图像和第二图像。存储缓冲器存储第二图像的图像数据。存储缓冲器包括：数据移位硬件机构，当处理器将第一图像的片段与第二图像的片段进行比较时，使用存储缓冲器内的硬件的数据移位机制将至少一部分条带移动到存储缓冲区。数据移位硬件机构优选地包括具有来自存储缓冲器内的相邻和非相邻数据列的相应可选择输入的数字多路复用器以及来自存储缓冲器内的相邻数据行的可选输入。

10. 发明申请

US20080239393A1 Cyclical Image Buffer 有权
标题翻译：循环图像缓冲区
公开(公告)号：US20080239393A1
公开(公告)日：2008-10-02
申请号：US11692941
申请日：2007-03-29
申请人： Mois Navon
发明人： Mois Navon
IPC分类号： G06F1/00
CPC分类号： G06T7/593 , G06T2200/28 , G06T2207/10012 , H04N13/10
摘要： A storage buffer attached to an image processor for stereo image processing. The processor compares a first image and a second image. The storage buffer stores image data of the second image. The storage buffer includes: a data-shifting-hardware mechanism which while the processor compares a patch of the first image to a swath of the second image, the data shifting mechanism using hardware within the storage buffer shifts at least a portion of the swath within the storage buffer. The data-shifting hardware mechanism includes preferably digital multiplexers with respective selectable inputs from adjacent and non-adjacent columns of data within the storage buffer and selectable inputs from adjacent rows of data within the storage buffer.
摘要翻译：连接到图像处理器以用于立体图像处理的存储缓冲器。处理器比较第一图像和第二图像。存储缓冲器存储第二图像的图像数据。存储缓冲器包括：数据移位硬件机构，当处理器将第一图像的片段与第二图像的片段进行比较时，使用存储缓冲器内的硬件的数据移位机制将至少一部分条带移动到存储缓冲区。数据移位硬件机构优选地包括具有来自存储缓冲器内的相邻和非相邻数据列的相应可选择输入的数字多路复用器以及来自存储缓冲器内的相邻数据行的可选输入。

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