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1. 发明授权

US08970041B2 Co-axial restraint for connectors within flip-chip packages 有权
标题翻译：倒装芯片封装内连接器的同轴约束
公开(公告)号：US08970041B2
公开(公告)日：2015-03-03
申请号：US13470379
申请日：2012-05-14
申请人： Mukta G. Farooq , John A. Fitzsimmons
发明人： Mukta G. Farooq , John A. Fitzsimmons
IPC分类号： H01L23/48 , H01L23/00
CPC分类号： H01L24/73 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/92 , H01L2224/10126 , H01L2224/1182 , H01L2224/13014 , H01L2224/13076 , H01L2224/131 , H01L2224/13111 , H01L2224/13565 , H01L2224/13582 , H01L2224/1369 , H01L2224/16225 , H01L2224/16227 , H01L2224/29014 , H01L2224/2919 , H01L2224/32225 , H01L2224/73104 , H01L2224/81097 , H01L2224/81191 , H01L2224/81801 , H01L2224/83191 , H01L2224/83855 , H01L2224/9211 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/30107 , H01L2924/351 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.
摘要翻译：组件可以包括微电子元件，例如具有其中制造的电路和半导体器件的半导体元件，以及多个电连接器，例如附接到微电子元件的触点的焊球。连接器可以被可压缩介电材料的第一内部区域200和介电材料的第二外部区域包围。在一个实施例中，底部填充物可以在相应的连接器或第二区域之间接触微电子元件的面。第二区域可以提供约束力，使得在连接器的体积膨胀期间，第一区域可以抵抗第二区域的约束力而被压缩。

2. 发明授权

US08962448B2 Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier 有权
标题翻译：用用于制造使用界面晶片作为永久载体的3D集成电路器件的程序编码的计算机可读介质
公开(公告)号：US08962448B2
公开(公告)日：2015-02-24
申请号：US13572004
申请日：2012-08-10
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/46
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
摘要翻译：提供了一种计算机可读介质，其由包括用于执行制造3D集成电路结构的方法的指令的程序编码。提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。第一有源电路层晶片被结合到界面晶片。然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

3. 发明授权

US08859390B2 Structure and method for making crack stop for 3D integrated circuits 有权
标题翻译：三维集成电路裂纹停止的结构和方法
公开(公告)号：US08859390B2
公开(公告)日：2014-10-14
申请号：US12700841
申请日：2010-02-05
申请人： Mukta G Farooq , John A Griesemer , William F Landers , Ian D Melville , Thomas M Shaw , Huilong Zhu
发明人： Mukta G Farooq , John A Griesemer , William F Landers , Ian D Melville , Thomas M Shaw , Huilong Zhu
IPC分类号： H01L23/58 , H01L25/065 , H01L21/78 , H01L23/48 , H01L23/00 , H01L21/768 , H01L23/31 , H01L21/20
CPC分类号： H01L23/5226 , H01L21/2007 , H01L21/76898 , H01L21/78 , H01L23/3114 , H01L23/481 , H01L23/53214 , H01L23/53228 , H01L23/562 , H01L23/585 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.
摘要翻译：公开了一种用于防止裂纹传播到3D集成电路的有源区域的结构，例如由薄化的衬底层或接合层的外围处的缺陷引发的裂纹及其形成方法。

4. 发明授权

US08692246B2 Leakage measurement structure having through silicon vias 有权
标题翻译：泄漏测量结构通过硅通孔
公开(公告)号：US08692246B2
公开(公告)日：2014-04-08
申请号：US13233085
申请日：2011-09-15
申请人： Bhavana Bhoovaraghan , Mukta G. Farooq , Emily R. Kinser , Sudesh Saroop
发明人： Bhavana Bhoovaraghan , Mukta G. Farooq , Emily R. Kinser , Sudesh Saroop
IPC分类号： H01L23/58 , H01L29/10 , G01R31/26 , H01L21/66
CPC分类号： H01L22/34 , H01L23/481 , H01L23/58 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate.
摘要翻译：一种用于通过衬底通孔的泄漏测量结构，其包括半导体衬底; 半导体衬底中的多个穿过衬底通孔，其基本上延伸穿过半导体衬底; 以及位于半导体衬底中的泄漏测量结构。泄漏测量结构包括延伸到半导体衬底中的多个衬底触点; 多个感测电路，连接到多个通过衬底通孔和多个衬底触点，所述多个感测电路提供指示来自多个通过衬底通孔的电流泄漏的多个输出; 一个内置的自检（BIST）引擎，逐步测试多个通过基板通孔; 以及耦合到BIST引擎以接收来自多个感测电路的输出的存储器。还包括测试半导体衬底的方法。

5. 发明授权

US08613996B2 Polymeric edge seal for bonded substrates 有权
标题翻译：粘合基材的聚合物边缘密封
公开(公告)号：US08613996B2
公开(公告)日：2013-12-24
申请号：US12603002
申请日：2009-10-21
申请人： Mukta G. Farooq , Thomas F. Houghton , Nitin Parbhoo , Richard P. Volant
发明人： Mukta G. Farooq , Thomas F. Houghton , Nitin Parbhoo , Richard P. Volant
IPC分类号： B32B7/00
CPC分类号： B32B37/1292 , B32B3/02 , B32B27/08 , B32B37/1284 , B32B2457/14 , H01L21/187 , Y10T156/10 , Y10T156/1064 , Y10T428/215 , Y10T428/219 , Y10T428/24355 , Y10T428/24752 , Y10T428/24777 , Y10T428/24802 , Y10T428/24851
摘要： A layer of polymer material is applied on a peripheral region of at least one of the two substrates to be bonded prior to bonding. The bonded structure formed thereby includes a first substrate, a second substrate in direct contact with the first substrate, and a ring of the polymer material in direct contact with the first substrate at a first interface and in direct contact with the second substrate. The ring of polymer material laterally surrounds and seals the interface at which the first substrate contacts the second substrate. A ring-shaped cavity can be formed within the polymeric ring. Alternately, the first interface and the second interface can be contiguous without a ring-shaped cavity between the first and second substrates.
摘要翻译：在接合之前，将待结合的两个基板中的至少一个的外围区域上施加一层聚合物材料。由此形成的接合结构包括第一基板，与第一基板直接接触的第二基板，以及在第一界面处与第一基板直接接触并与第二基板直接接触的聚合物材料的环。聚合物材料环横向包围并密封第一基底与第二基底接触的界面。可以在聚合物环内形成环形空腔。或者，第一界面和第二界面可以相邻，而在第一和第二基板之间没有环形腔。

6. 发明授权

US08610283B2 Semiconductor device having a copper plug 有权
标题翻译：具有铜插头的半导体装置
公开(公告)号：US08610283B2
公开(公告)日：2013-12-17
申请号：US12573183
申请日：2009-10-05
申请人： Mukta G. Farooq , Emily R. Kinser , Ian D. Melville , Krystyna Waleria Semkow
发明人： Mukta G. Farooq , Emily R. Kinser , Ian D. Melville , Krystyna Waleria Semkow
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/02697 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05016 , H01L2224/05026 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05157 , H01L2224/05187 , H01L2224/05562 , H01L2224/05572 , H01L2224/131 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/15787 , H01L2924/04953 , H01L2924/01014 , H01L2224/05552 , H01L2924/00
摘要： Disclosed is a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. In a further embodiment, there may also be an aluminum layer between the insulation layer and copper plug. Also disclosed is a process for making the semiconductor device.
摘要翻译：公开了一种半导体器件，其中绝缘层具有与器件的最后布线层接触的铜插塞。还可以存在将铜塞与绝缘层分离的阻挡层。在另一实施例中，在绝缘层和铜插塞之间也可以有铝层。还公开了制造半导体器件的方法。

7. 发明授权

US08609537B2 Integrated void fill for through silicon via 有权
标题翻译：通过硅通孔的集成空隙填充
公开(公告)号：US08609537B2
公开(公告)日：2013-12-17
申请号：US13555418
申请日：2012-07-23
申请人： Richard P. Volant , Mukta G. Farooq , Kevin S. Petrarca
发明人： Richard P. Volant , Mukta G. Farooq , Kevin S. Petrarca
IPC分类号： H01L25/11
CPC分类号： H01L21/76879 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/16 , H01L24/29 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/29 , H01L2224/29298 , H01L2224/9202 , H01L2224/92144 , H01L2225/06541 , H01L2225/06575 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/05552 , H01L2924/00
摘要： A microelectronic assembly and related method of forming a through hole extending through a first chip and a second chip are provided. The first and second chip have confronting faces, metallic features join the first and second chips leaving a gap chips. A first etch creates a hole through the first chip. The hole has a first wall extending in a vertical direction, and a second wall sloping inwardly from the first wall to an inner opening to expose the gap. Material of the first or second chips exposed within the hole is sputtered to form a wall in the gap. A second etch extends the hole into the second chip. An electrically conductive through silicon via can then be formed extending through the first chip, the wall between the chips and into the second chip.
摘要翻译：提供了形成贯穿第一芯片和第二芯片的通孔的微电子组件和相关方法。第一和第二芯片具有面对面，金属特征连接第一和第二芯片留下间隙芯片。第一蚀刻通过第一芯片产生孔。孔具有沿垂直方向延伸的第一壁和从第一壁向内倾斜到内部开口的第二壁，以露出间隙。暴露在孔内的第一或第二芯片的材料被溅射以在间隙中形成壁。第二蚀刻将孔延伸到第二芯片中。然后可以形成延伸穿过第一芯片，芯片之间的壁并进入第二芯片的导电硅通孔。

8. 发明授权

US08455270B2 3D multiple die stacking 失效
标题翻译： 3D多芯片堆叠
公开(公告)号：US08455270B2
公开(公告)日：2013-06-04
申请号：US12561618
申请日：2009-09-17
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L24/94 , H01L22/14 , H01L22/20 , H01L25/0657 , H01L2223/54426 , H01L2225/06596 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.
摘要翻译：形成三维（3D）模具的过程。针对通过（良好的模具）或失败（坏模具）预定测试标准的模具测试多个晶片。两个测试的晶片彼此靠近放置。以这样的方式对晶片进行对准，以便使两个晶片之间对准的良好裸片的数量最大化。然后将两个晶片结合在一起并切成多个粘结好的模具的各个叠层。

9. 发明授权

US08415238B2 Three dimensional integration and methods of through silicon via creation 有权
标题翻译：通过创建通过硅的三维集成和方法
公开(公告)号：US08415238B2
公开(公告)日：2013-04-09
申请号：US12687282
申请日：2010-01-14
申请人： Mukta G. Farooq , Emily R. Kinser , Richard Wise , Hakeem Yusuff
发明人： Mukta G. Farooq , Emily R. Kinser , Richard Wise , Hakeem Yusuff
IPC分类号： H01L21/425 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76847 , H01L21/0337 , H01L21/32136 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.
摘要翻译：一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露衬底层上的第一平面区域，蚀刻暴露的平面区域以形成在结构中具有第一深度的空腔，将光致抗蚀剂的第二部分去除在衬底层上露出第二平面区域，在第二平面区域中形成掺杂部分，并且蚀刻腔体以暴露结构中的第一导体和掺杂部分以暴露结构中的第二导体。

10. 发明授权

US08399180B2 Three dimensional integration with through silicon vias having multiple diameters 有权
标题翻译：具有多个直径的通过硅通孔的三维集成
公开(公告)号：US08399180B2
公开(公告)日：2013-03-19
申请号：US12687289
申请日：2010-01-14
申请人： Mukta G. Farooq , Ramona Kei , Emily R. Kinser , Anthony D. Lisi , Richard Wise , Hakeem Yusuff
发明人： Mukta G. Farooq , Ramona Kei , Emily R. Kinser , Anthony D. Lisi , Richard Wise , Hakeem Yusuff
IPC分类号： G03F7/26
CPC分类号： H01L21/76898 , H01L21/3085 , H01L25/0657 , H01L2225/06544 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.
摘要翻译：公开了一种方法，其包括在结构的衬底上图案化光致抗蚀剂层，去除光致抗蚀剂层的第一部分以暴露衬底的第一区域，蚀刻第一区域以形成具有第一深度的空腔，光致抗蚀剂的一部分以暴露衬底的附加区域，并且蚀刻该腔以暴露结构中的第一导体和附加区域以暴露该结构中的第二导体。

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