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1. 发明授权

US08450782B2 Field effect transistor, method of manufacturing field effect transistor, and method of forming groove 有权
标题翻译：场效应晶体管，制造场效应晶体管的方法和形成沟槽的方法
公开(公告)号：US08450782B2
公开(公告)日：2013-05-28
申请号：US13075843
申请日：2011-03-30
申请人： Yoshihiro Sato , Takehiko Nomura , Nariaki Ikeda , Takuya Kokawa , Masayuki Iwami , Sadahiro Kato
发明人： Yoshihiro Sato , Takehiko Nomura , Nariaki Ikeda , Takuya Kokawa , Masayuki Iwami , Sadahiro Kato
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L29/4232 , H01L29/518 , H01L29/66462 , H01L29/7787
摘要： A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm−3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.
摘要翻译：场效应晶体管包括在基板上的高电阻层，形成在高电阻层上并具有碳浓度不大于1×10 18 cm -3且具有层厚度的沟道层的半导体操作层大于10nm且不大于100nm的凹槽，形成在半导体操作层中的沟道层内部的凹部，形成在半导体操作层上的沟槽间的沟槽间的沟槽间的沟槽，栅极绝缘膜，其形成在半导体操作层上以覆盖凹部;以及栅电极，其形成在凹部中的栅极绝缘膜上。

2. 发明申请

US20100117186A1 Semiconductor device and method of producing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100117186A1
公开(公告)日：2010-05-13
申请号：US12457904
申请日：2009-06-24
申请人： Hiroshi Kambayashi , Shusuke Kaya , Nariaki Ikeda
发明人： Hiroshi Kambayashi , Shusuke Kaya , Nariaki Ikeda
IPC分类号： H01L29/47 , H01L21/28 , H01L21/82
CPC分类号： H01L29/0657 , H01L29/2003 , H01L29/402 , H01L29/42316 , H01L29/475 , H01L29/66462 , H01L29/7787
摘要： The invention provides a semiconductor device and a method for fabricating the same capable of preventing a field plate portion from being delaminated from an insulating film by stress inherent in a semiconductor layer even if the stress is released in forming a trench in part of the semiconductor layer where the semiconductor device is to be separated and capable of having a higher breakdown property of the semiconductor device. The semiconductor device has source, drain and gate electrodes, insulating films that insulate the electrodes on an electron supplying layer and a mesa-structure formed at part where the semiconductor device is to be separated. The gate electrode has a first electrode layer having a function of the electrode and a second electrode layer having a field plate portion whose part that contacts with the insulating film is made of a metallic material that adheres well to the insulating film.
摘要翻译：本发明提供一种半导体器件及其制造方法，其能够通过半导体层中固有的应力防止场板部分与绝缘膜分层，即使在半导体层的一部分中形成沟槽时释放应力其中半导体器件将被分离并且能够具有较高的半导体器件的击穿特性。半导体器件具有源极，漏极和栅极电极，使电极在电子供给层上绝缘的绝缘膜和在半导体器件将被分离的部分处形成的台面结构。栅电极具有具有电极功能的第一电极层和具有场板部分的第二电极层，其与绝缘膜接触的部分由与绝缘膜良好结合的金属材料制成。

3. 发明授权

US08525225B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08525225B2
公开(公告)日：2013-09-03
申请号：US11511293
申请日：2006-08-29
申请人： Hiroshi Kambayashi , Nariaki Ikeda , Seikoh Yoshida
发明人： Hiroshi Kambayashi , Nariaki Ikeda , Seikoh Yoshida
IPC分类号： H01L29/739
CPC分类号： H01L29/7787 , H01L23/3171 , H01L29/2003 , H01L2924/0002 , H01L2924/13063 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device includes a plurality of electrodes arranged on a compound semiconductor layer grown on a substrate, and a surface protection film that protects a surface of a semiconductor layer on the compound semiconductor layer between the electrodes. A refractive index of the surface protection film is controlled so that a stress caused by the surface protection film on the surface of the semiconductor layer is minimized.
摘要翻译：半导体器件包括布置在生长在衬底上的化合物半导体层上的多个电极以及保护电极之间的化合物半导体层上的半导体层的表面的表面保护膜。控制表面保护膜的折射率使得由半导体层表面上的表面保护膜引起的应力最小化。

4. 发明授权

US08035128B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08035128B2
公开(公告)日：2011-10-11
申请号：US12580015
申请日：2009-10-15
申请人： Nariaki Ikeda , Shusuke Kaya
发明人： Nariaki Ikeda , Shusuke Kaya
IPC分类号： H01L29/739
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/4236 , H01L29/42376 , H01L29/66462
摘要： There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.
摘要翻译：提供一种半导体器件及其制造方法，其耐受特性可以增强并且其导通电阻可能降低。 MIS型HEMT包括由III族氮化物半导体形成并形成在支撑基板上的载流子行进层，由III族氮化物半导体形成并形成在载流子行进层上的载流子供应层，形成的源极和漏极在载体供给层上，形成在载体供给层上的绝缘膜和形成在绝缘膜上的栅电极。绝缘膜形成在介于源电极和漏电极之间的区域中，并且具有横截面为倒梯形并且其上开口比其底部更宽的沟槽。栅电极至少从沟槽的底部形成在漏电极侧的绝缘膜上。

5. 发明申请

US20100117146A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100117146A1
公开(公告)日：2010-05-13
申请号：US12580015
申请日：2009-10-15
申请人： Nariaki Ikeda , Shusuke Kaya
发明人： Nariaki Ikeda , Shusuke Kaya
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/4236 , H01L29/42376 , H01L29/66462
摘要： There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.
摘要翻译：提供一种半导体器件及其制造方法，其耐受特性可以增强并且其导通电阻可能降低。 MIS型HEMT包括由III族氮化物半导体形成并形成在支撑基板上的载流子行进层，由III族氮化物半导体形成并形成在载流子行进层上的载流子供应层，形成的源极和漏极在载体供给层上，形成在载体供给层上的绝缘膜和形成在绝缘膜上的栅电极。绝缘膜形成在介于源电极和漏电极之间的区域中，并且具有横截面为倒梯形并且其上开口比其底部更宽的沟槽。栅电极至少从沟槽的底部形成在漏电极侧的绝缘膜上。

6. 发明授权

US06911713B2 Optical device having a carrier-depleted layer 失效
标题翻译：具有载流子耗尽层的光学器件
公开(公告)号：US06911713B2
公开(公告)日：2005-06-28
申请号：US10617661
申请日：2003-07-14
申请人： Nariaki Ikeda , Takeharu Yamaguchi , Satoshi Arakawa , Nobumitsu Yamanaka , Akihiko Kasukawa , Ryusuke Nakasaki
发明人： Nariaki Ikeda , Takeharu Yamaguchi , Satoshi Arakawa , Nobumitsu Yamanaka , Akihiko Kasukawa , Ryusuke Nakasaki
IPC分类号： G02F1/017 , H01S5/026 , H01S5/12 , H01S5/22 , H01S5/34 , H01S5/343 , H01L31/00
CPC分类号： B82Y20/00 , H01S5/0265 , H01S5/12 , H01S5/2222 , H01S5/2224 , H01S5/2226 , H01S5/3072 , H01S5/3409 , H01S5/34306
摘要： An EA-DFB module including a DFB laser diode and an EA modulator formed on an InP first-conductivity-type substrate has a mesa stripe, a current blocking structure formed on both side surfaces of the mesa strip and a second InP cladding layer formed on top of the mesa stripe and the current blocking structure. The current blocking structure includes a Fe-doped semi-insulating film, a first conductivity-type buried layer and a carrier-depleted layer. The carrier-depleted layer reduces the parasitic capacitance at the boundary between the first-conductivity-type buried layer and the second InP cladding layer.
摘要翻译：包括形成在InP第一导电型基板上的DFB激光二极管和EA调制器的EA-DFB模块具有台面条状，形成在台面条的两侧表面上的电流阻挡结构和形成在第一导电型基板上的第二InP包层台面条纹和当前阻挡结构的顶部。电流阻挡结构包括掺杂Fe的半绝缘膜，第一导电型掩埋层和载流子耗尽层。载流子耗尽层降低了第一导电型掩埋层和第二InP包覆层之间的边界处的寄生电容。

7. 发明授权

US08729603B2 GaN-based semiconductor element 有权
标题翻译： GaN基半导体元件
公开(公告)号：US08729603B2
公开(公告)日：2014-05-20
申请号：US13444936
申请日：2012-04-12
申请人： Nariaki Ikeda , Seikoh Yoshida
发明人： Nariaki Ikeda , Seikoh Yoshida
IPC分类号： H01L29/205
CPC分类号： H01L29/452 , H01L29/10 , H01L29/2003 , H01L29/41766 , H01L29/423 , H01L29/66462 , H01L29/7787
摘要： A GaN-based semiconductor element includes a substrate, a buffer layer formed on the substrate, including an electrically conductive portion, an epitaxial layer formed on the buffer layer, and a metal structure in ohmic contact with the electrically conductive portion of the buffer layer for controlling an electric potential of the buffer layer.
摘要翻译： GaN基半导体元件包括衬底，形成在衬底上的缓冲层，包括导电部分，形成在缓冲层上的外延层，以及与缓冲层的导电部分欧姆接触的金属结构，控制缓冲层的电位。

8. 发明授权

US08304774B2 Transistor and method for fabricating the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08304774B2
公开(公告)日：2012-11-06
申请号：US12705112
申请日：2010-02-12
申请人： Shusuke Kaya , Nariaki Ikeda , Jiang Li
发明人： Shusuke Kaya , Nariaki Ikeda , Jiang Li
IPC分类号： H01L29/04
CPC分类号： H01L29/7787 , H01L29/0657 , H01L29/2003 , H01L29/402 , H01L29/41758 , H01L29/42316
摘要： The invention provides a transistor having a leak current between a source and drain in a nitride compound semiconductor formed on a substrate that is reduced. A gate electrode, a source electrode and a drain electrode are formed respectively on the surface of the nitride compound semiconductor formed on the silicon substrate in the transistor. At least one of the source electrode and the drain electrode is surrounded by an auxiliary electrode connected with the gate electrode. Because a depletion layer is formed in the nitride compound semiconductor under the auxiliary electrode, a route of the leak current is shut off and the leak current between the source and drain may be effectively reduced.
摘要翻译：本发明提供一种晶体管，其在形成在基板上的氮化物化合物半导体中的源极和漏极之间具有漏电流，所述氮化物半导体被还原。分别在形成在晶体管的硅衬底上的氮化物化合物半导体的表面上形成栅电极，源电极和漏电极。源电极和漏电极中的至少一个被与栅电极连接的辅助电极包围。由于在辅助电极下方的氮化物化合物半导体中形成耗尽层，所以可以切断泄漏电流的路径，能够有效地降低源极与漏极之间的漏电流。

9. 发明申请

US20120193639A1 GaN-BASED SEMICONDUCTOR ELEMENT 有权
标题翻译： GaN基半导体元件
公开(公告)号：US20120193639A1
公开(公告)日：2012-08-02
申请号：US13444936
申请日：2012-04-12
申请人： Nariaki IKEDA , Seikoh YOSHIDA
发明人： Nariaki IKEDA , Seikoh YOSHIDA
IPC分类号： H01L29/20
CPC分类号： H01L29/452 , H01L29/10 , H01L29/2003 , H01L29/41766 , H01L29/423 , H01L29/66462 , H01L29/7787
摘要： A GaN-based semiconductor element includes a substrate, a buffer layer formed on the substrate, including an electrically conductive portion, an epitaxial layer formed on the buffer layer, and a metal structure in ohmic contact with the electrically conductive portion of the buffer layer for controlling an electric potential of the buffer layer.
摘要翻译： GaN基半导体元件包括衬底，形成在衬底上的缓冲层，包括导电部分，形成在缓冲层上的外延层，以及与缓冲层的导电部分欧姆接触的金属结构，控制缓冲层的电位。

10. 发明申请

US20110316048A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110316048A1
公开(公告)日：2011-12-29
申请号：US13225299
申请日：2011-09-02
申请人： Nariaki Ikeda , Shusuke Kaya
发明人： Nariaki Ikeda , Shusuke Kaya
IPC分类号： H01L29/78
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/4236 , H01L29/42376 , H01L29/66462
摘要： There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode.
摘要翻译：提供一种半导体器件及其制造方法，其耐受特性可以增强并且其导通电阻可能降低。 MIS型HEMT包括由III族氮化物半导体形成并形成在支撑基板上的载流子行进层，由III族氮化物半导体形成并形成在载流子行进层上的载流子供应层，形成的源极和漏极在载体供给层上，形成在载体供给层上的绝缘膜和形成在绝缘膜上的栅电极。绝缘膜形成在介于源电极和漏电极之间的区域中，并且具有横截面为倒梯形并且其上开口比其底部更宽的沟槽。栅电极至少从沟槽的底部形成在漏电极侧的绝缘膜上。

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