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1. 发明授权

US09766966B1 Method and apparatus for on-chip adjustment of chip characteristics 有权
公开(公告)号：US09766966B1
公开(公告)日：2017-09-19
申请号：US13334831
申请日：2011-12-22
申请人： Neal C. Jaarsma
发明人： Neal C. Jaarsma
IPC分类号： G01R31/02 , G01R31/26 , G06F11/07
CPC分类号： G06F11/079 , H01L22/14 , H01L22/20
摘要： Systems and methods are provided for optimizing operation of an integrated circuit. In one implementation, a system is provided for optimizing operation of an integrated circuit by adjusting an operational parameter of the integrated circuit based on a reference count stored in non-volatile memory fabricated on the integrated circuit. In another implementation, a method is provided for optimizing operation of an integrated circuit by generating, during operation of the integrated circuit, a first oscillator count of an oscillator, comparing the first oscillator count with at least one reference count stored on the integrated circuit, and activating, a control circuit to adjust an operational parameter of the integrated circuit based on a result of the comparison.

2. 发明授权

US08159241B1 Method and apparatus for on-chip adjustment of chip characteristics 有权
标题翻译：用于芯片特性片上调整的方法和装置
公开(公告)号：US08159241B1
公开(公告)日：2012-04-17
申请号：US12107466
申请日：2008-04-22
申请人： Neal C. Jaarsma
发明人： Neal C. Jaarsma
IPC分类号： G01R31/00
CPC分类号： G06F11/079 , H01L22/14 , H01L22/20
摘要： Systems and methods are provided for optimizing operation of an integrated circuit. In one implementation, a system is provided for optimizing operation of an integrated circuit by adjusting an operational parameter of the integrated circuit based on a reference count stored in non-volatile memory fabricated on the integrated circuit. In another implementation, a method is provided for optimizing operation of an integrated circuit by generating, during operation of the integrated circuit, a first oscillator count of an oscillator, comparing the first oscillator count with at least one reference count stored on the integrated circuit, and activating, a control circuit to adjust an operational parameter of the integrated circuit based on a result of the comparison.
摘要翻译：提供了用于优化集成电路的操作的系统和方法。在一个实现中，提供了一种用于通过基于存储在集成电路上制造的非易失性存储器中的参考计数来调整集成电路的操作参数来优化集成电路的操作的系统。在另一实施方案中，提供了一种用于优化集成电路的操作的方法，所述方法在所述集成电路的操作期间产生振荡器的第一振荡器计数，将所述第一振荡器计数与存储在所述集成电路上的至少一个参考计数进行比较，以及激活控制电路，以根据所述比较的结果来调整所述集成电路的操作参数。

3. 发明授权

US5130989A Serial and parallel scan technique for improved testing of systolic arrays 失效
标题翻译：串并行扫描技术，用于改善收缩阵列的测试
公开(公告)号：US5130989A
公开(公告)日：1992-07-14
申请号：US494016
申请日：1990-03-15
申请人： Daryl E. Anderson , Ralph H. Lanham , Neal C. Jaarsma
发明人： Daryl E. Anderson , Ralph H. Lanham , Neal C. Jaarsma
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3185 , G06F11/22 , G11C29/00 , G11C29/02 , G11C29/56
CPC分类号： G01R31/318516
摘要： A method for testing a systolic array in which a plurality of sequential registers is each connected to the rest by an intervening logic component. Each register includes a plurality of memory elements. Each register can be enabled to act as a latch register whereby digital data is loaded into an output therefrom in parallel or as a shift register whereby digital data is shifted sequentially in each register from one memory element to the next adjacent memory element. A test vector consisting of a preselected string of digital data is shifted in parallel into each of the registers. The test vector in each register is loaded into the associated logic component which operates on the vector and stores the data in the next adjacent register. The resulting data is serially clocked from each register onto unique bus nodes and examined in parallel to determine whether or not the expected result was obtained.
摘要翻译：一种用于测试心脏阵列的方法，其中多个顺序寄存器各自通过中间的逻辑组件连接到其余的。每个寄存器包括多个存储元件。每个寄存器可以被用作锁存寄存器，由此数字数据被并行地加载到其输出中，或者作为移位寄存器，由此数字数据在每个寄存器中从一个存储元件顺序地移位到下一个相邻的存储元件。由预选的数字数据串组成的测试向量并行移位到每个寄存器中。每个寄存器中的测试向量被加载到相关联的逻辑组件中，该组件对向量进行操作并将数据存储在下一个相邻寄存器中。所得到的数据从每个寄存器被串行计时到独特的总线节点上并行检查以确定是否获得预期的结果。

4. 发明授权

US06751768B2 Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits 有权
标题翻译：分层创建用于片上系统电路的静态电流（IDDQ）测试的向量
公开(公告)号：US06751768B2
公开(公告)日：2004-06-15
申请号：US09997658
申请日：2001-11-29
申请人： Fidel Muradali , Neal C. Jaarsma , Chinsong Sul , Garrett O'Brien
发明人： Fidel Muradali , Neal C. Jaarsma , Chinsong Sul , Garrett O'Brien
IPC分类号： G06F1100
CPC分类号： G01R31/3008
摘要： A method is presented for generating test vectors for an integrated circuit. Input test vectors and output test vectors are generated for non-core cell portions of the integrated circuit. Input test vectors and output test vectors are generated for core cell partitions of the integrated circuit. The input test vectors for the non-core cell portions and the input test vectors for the core cell partitions are combined into a single combined input test vector.
摘要翻译：提出了一种用于生成集成电路测试向量的方法。为集成电路的非核心单元部分生成输入测试向量和输出测试向量。为集成电路的核心单元分区生成输入测试向量和输出测试向量。非核心单元部分的输入测试向量和核心单元分区的输入测试向量被组合成单个组合输入测试向量。

5. 发明授权

US06587981B1 Integrated circuit with scan test structure 有权
标题翻译：具有扫描测试结构的集成电路
公开(公告)号：US06587981B1
公开(公告)日：2003-07-01
申请号：US09450469
申请日：1999-11-29
申请人： Fidel Muradali , Neal C. Jaarsma
发明人： Fidel Muradali , Neal C. Jaarsma
IPC分类号： G01R3128
CPC分类号： G01R31/318555 , G01R31/318558
摘要： Scan path structures are provided for integrated circuits which contain one or more cores or levels of sub-cores embedded within the cores. Circuitry is provided to permit scan testing of scan elements, such as scan wrapper cells and scan chains, in the cores and sub-cores by providing scan paths which share access to limited numbers of scan test ports of the integrated circuit under test. This solves the problem of having sufficient scan ports at the integrated circuit boundaries for the increasingly higher number of scan paths which require access to these scan ports.
摘要翻译：为集成电路提供扫描路径结构，该集成电路包含一个或多个内核或核心级别的核心。提供电路以通过提供共享对被测集成电路的有限数量的扫描测试端口的访问的扫描路径来允许对核心和子核心中的扫描元件（例如扫描包装单元和扫描链）进行扫描测试。这解决了在集成电路边界具有足够的扫描端口以满足需要访问这些扫描端口的越来越多数量的扫描路径的问题。

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