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1. 发明授权

US09438418B1 Systems and methods for generating a key difficult to clone 有权
标题翻译：用于生成难以克隆的密钥的系统和方法
公开(公告)号：US09438418B1
公开(公告)日：2016-09-06
申请号：US13102673
申请日：2011-05-06
申请人： Bruce B. Pedersen , Ninh D. Ngo
发明人： Bruce B. Pedersen , Ninh D. Ngo
IPC分类号： H04L9/08 , H04L29/06 , H04L9/14
CPC分类号： H04L9/0861 , G09C1/00 , H04L9/14 , H04L9/3239 , H04L63/0478 , H04L63/06
摘要： Systems and methods relating to generating a key that is difficult to clone are described. The methods include receiving a programmable logic device (PLD) with a first key and applying a one-way hash function to a second key or the first key and the second key to create a third key. The application of the one-way hash function is performed using one or more components hardwired into the PLD. The methods further include storing the third key in the PLD only after using the one or more components to apply the one-way hash function.
摘要翻译：描述与生成难以克隆的密钥有关的系统和方法。所述方法包括用第一密钥接收可编程逻辑器件（PLD），并将单向散列函数应用于第二密钥或第一密钥和第二密钥以创建第三密钥。单向散列函数的应用使用硬连线到PLD中的一个或多个组件来执行。所述方法还包括仅在使用所述一个或多个组件来应用所述单向散列函数之后将所述第三密钥存储在所述PLD中。

2. 发明申请

US20070283193A1 SOFT ERROR LOCATION AND SENSITIVITY DETECTION FOR PROGRAMMABLE DEVICES 有权
标题翻译：可编程器件的软错误位置和灵敏度检测
公开(公告)号：US20070283193A1
公开(公告)日：2007-12-06
申请号：US11737089
申请日：2007-04-18
申请人： David Lewis , Ninh D. Ngo , Andy L. Lee , Joseph Huang
发明人： David Lewis , Ninh D. Ngo , Andy L. Lee , Joseph Huang
IPC分类号： G06F11/10
CPC分类号： G11C29/52 , G06F11/1064 , H03K19/17764
摘要： Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a sensitivity processor. The error detection circuit detects the presence of errors. The sensitivity processor determines whether a detected error can be ignored, or whether remedial action, such as providing an error flag, reconfiguring the device, or correcting the error, should be commenced. The sensitivity processor may make this determination based on whether the error occurred in a memory cell that configures unused circuitry. The sensitivity processor may make use of an error log to track known errors that may be ignored, so that this determination does not need to be done each time the configuration data is checked.
摘要翻译：检测在存储的配置数据中发生的软错误是否可以被忽略的假阳性的电路，方法和装置，使得不必要地重新加载配置数据或其他补救措施。一个例子提供了包括错误检测电路和灵敏度处理器的集成电路。误差检测电路检测出错误。灵敏度处理器确定是否可以忽略检测到的错误，或者是否开始补救措施，例如提供错误标志，重新配置设备或纠正错误。灵敏度处理器可以基于是否在配置未使用的电路的存储器单元中发生错误来进行该确定。灵敏度处理器可以使用错误日志来跟踪可能被忽略的已知错误，使得每次检查配置数据时不需要完成该确定。

3. 发明授权

US09172505B1 Methods and apparatus for frame detection 有权
标题翻译：帧检测方法和装置
公开(公告)号：US09172505B1
公开(公告)日：2015-10-27
申请号：US13624095
申请日：2012-09-21
申请人： Haiyun Yang , Ninh D. Ngo
发明人： Haiyun Yang , Ninh D. Ngo
IPC分类号： H04L1/00 , H04L25/02
CPC分类号： H04L1/0091 , H03M13/333 , H04L1/0041 , H04L25/0262
摘要： One embodiment relates to a frame detection circuit for detecting a frame boundary. The circuit includes at least two frame buffers and a staged-parallel structure of syndrome computation circuits that computes a number of syndromes in one cycle. The two frame buffers are each one word in width. The number of syndromes computed in one cycle by the cascaded series is a fraction of a number of bits in one word. Another embodiment relates to a method for detecting a frame boundary. Another embodiment relates to a method for computing a current syndrome. Other embodiments, aspects, and features are also disclosed.
摘要翻译：一个实施例涉及用于检测帧边界的帧检测电路。该电路包括至少两个帧缓冲器和在一个周期中计算多个综合征的校正子计算电路的分段并行结构。两个帧缓冲区的宽度各为一个字。通过级联序列在一个周期中计算的综合征数量是一个字中位数的几分之一。另一实施例涉及一种用于检测帧边界的方法。另一实施例涉及一种用于计算当前综合征的方法。还公开了其它实施例，方面和特征。

4. 发明授权

US08694864B1 Parallel processing error detection and location circuitry for configuration random-access memory 有权
公开(公告)号：US08694864B1
公开(公告)日：2014-04-08
申请号：US13617745
申请日：2012-09-14
申请人： Ninh D. Ngo
发明人： Ninh D. Ngo
IPC分类号： G11C29/00
CPC分类号： H03M13/1525 , G06F11/1004 , G11C7/1006 , G11C2029/0411
摘要： Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

5. 发明申请

US20130162290A1 PARTIAL RECONFIGURATION CIRCUITRY 有权
标题翻译：部分重构电路
公开(公告)号：US20130162290A1
公开(公告)日：2013-06-27
申请号：US13481506
申请日：2012-05-25
申请人： Balaji Margabandu , Dirk A. Reese , Leo Min Maung , Ninh D. Ngo
发明人： Balaji Margabandu , Dirk A. Reese , Leo Min Maung , Ninh D. Ngo
IPC分类号： H03K19/173
CPC分类号： H03K19/17756 , H03K19/1776
摘要： Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame.
摘要翻译：集成电路可以包括用于重新配置存储器阵列的一部分的部分重配置（PR）电路。 PR电路可以包括主机电路，控制电路，地址寄存器以及第一，第二和第三数据寄存器。主机电路可以向控制电路发送一系列PR指令。控制电路可以包括用于解压缩压缩指令的解压缩电路，用于解密加密指令的解密电路，用于检测指令中的错误的错误检查电路和逻辑电路。地址寄存器可以选择所需的帧。所选择的帧可以被加载到第三数据寄存器中。第三数据寄存器的内容可以被移位到第一数据寄存器中。可以使用移入第二数据寄存器的逻辑电路根据期望的逻辑功能修改第一数据寄存器的内容，并写入所选择的帧。

6. 发明授权

US08130574B2 Error detection on programmable logic resources 有权
标题翻译：可编程逻辑资源的错误检测
公开(公告)号：US08130574B2
公开(公告)日：2012-03-06
申请号：US13024666
申请日：2011-02-10
申请人： Ninh D. Ngo , Andy L. Lee , Kerry Veenstra
发明人： Ninh D. Ngo , Andy L. Lee , Kerry Veenstra
IPC分类号： G11C29/00
CPC分类号： H03K19/17764 , G06F11/1004
摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.
摘要翻译：在可编程逻辑资源上提供错误检测电路。可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。在另一个实施例中，期望值可以包括在校验和计算中。可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。该输出可以被发送到用户逻辑可访问的输出引脚。

7. 发明申请

US20110138240A1 ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES 有权
标题翻译：对可编程逻辑资源的错误检测
公开(公告)号：US20110138240A1
公开(公告)日：2011-06-09
申请号：US13024666
申请日：2011-02-10
申请人： Ninh D. Ngo , Andy L. Lee , Kerry Veenstra
发明人： Ninh D. Ngo , Andy L. Lee , Kerry Veenstra
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： H03K19/17764 , G06F11/1004
摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.
摘要翻译：在可编程逻辑资源上提供错误检测电路。可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。在另一个实施例中，期望值可以包括在校验和计算中。可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。该输出可以被发送到用户逻辑可访问的输出引脚。

8. 发明授权

US07702978B2 Soft error location and sensitivity detection for programmable devices 有权
标题翻译：可编程器件的软错误位置和灵敏度检测
公开(公告)号：US07702978B2
公开(公告)日：2010-04-20
申请号：US11737089
申请日：2007-04-18
申请人： David Lewis , Ninh D. Ngo , Andy L. Lee , Joseph Huang
发明人： David Lewis , Ninh D. Ngo , Andy L. Lee , Joseph Huang
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G11C29/52 , G06F11/1064 , H03K19/17764
摘要： Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a sensitivity processor. The error detection circuit detects the presence of errors. The sensitivity processor determines whether a detected error can be ignored, or whether remedial action, such as providing an error flag, reconfiguring the device, or correcting the error, should be commenced. The sensitivity processor may make this determination based on whether the error occurred in a memory cell that configures unused circuitry. The sensitivity processor may make use of an error log to track known errors that may be ignored, so that this determination does not need to be done each time the configuration data is checked.
摘要翻译：检测在存储的配置数据中发生的软错误是否可以被忽略的假阳性的电路，方法和装置，使得不必要地重新加载配置数据或其他补救措施。一个例子提供了包括错误检测电路和灵敏度处理器的集成电路。误差检测电路检测出错误。灵敏度处理器确定是否可以忽略检测到的错误，或者是否开始补救措施，例如提供错误标志，重新配置设备或纠正错误。灵敏度处理器可以基于是否在配置未使用的电路的存储器单元中发生错误来进行该确定。灵敏度处理器可以使用错误日志来跟踪可能被忽略的已知错误，使得每次检查配置数据时不需要完成该确定。

9. 发明授权

US07310757B2 Error detection on programmable logic resources 有权
标题翻译：可编程逻辑资源的错误检测
公开(公告)号：US07310757B2
公开(公告)日：2007-12-18
申请号：US10270711
申请日：2002-10-10
申请人： Ninh D. Ngo , Andy L. Lee , Kerry Veenstra
发明人： Ninh D. Ngo , Andy L. Lee , Kerry Veenstra
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： H03K19/17764 , G06F11/1004
摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.
摘要翻译：在可编程逻辑资源上提供错误检测电路。可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。在另一个实施例中，期望值可以包括在校验和计算中。可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。该输出可以被发送到用户逻辑可访问的输出引脚。

10. 发明授权

US08661321B1 Parallel processing error detection and location circuitry for configuration random-access memory 失效
标题翻译：用于配置随机存取存储器的并行处理错误检测和位置电路
公开(公告)号：US08661321B1
公开(公告)日：2014-02-25
申请号：US13618097
申请日：2012-09-14
申请人： Ninh D. Ngo
发明人： Ninh D. Ngo
IPC分类号： G11C29/00
CPC分类号： H03M13/1525 , G06F11/1004 , G11C7/1006 , G11C2029/0411
摘要： Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.
摘要翻译：提供错误检测和错误位置确定电路，用于检测和定位可编程集成电路上的随机存取存储器阵列中的软错误。随机存取存储器阵列包含随机访问存储器单元的行和列。一些单元载入配置数据，并产生用于编程可编程逻辑的相关区域的静态输出信号。对阵列的每列计算循环冗余校验错误校正位。循环冗余校验错误校正位存储在阵列中相应的单元格列中。在系统中的集成电路的正常操作期间，单元受到由背景辐射引起的软错误。错误检测和错误位置确定电路使用并行处理来连续监视数据以识别每个错误的行和列位置。

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