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1. 发明授权

US08762615B2 Dequeue operation using mask vector to manage input/output interruptions 失效
标题翻译：使用掩码向量的出队操作来管理输入/输出中断
公开(公告)号：US08762615B2
公开(公告)日：2014-06-24
申请号：US13332427
申请日：2011-12-21
申请人： Janet R. Easton , Norbert Hagspiel , Bernd Nerz
发明人： Janet R. Easton , Norbert Hagspiel , Bernd Nerz
IPC分类号： G06F9/48
CPC分类号： G06F13/24
摘要： A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.
摘要翻译：发出命令以重置一个或多个待处理的中断指示符并仲裁中断的所有权。响应于接收到该命令的处理器，检查所选待处理的中断指示符。如果未设置所选待处理的中断指示符，则会检查另一个未决中断指示符，而不是提供否定响应并重新发出命令。以这种方式，一个出队命令可以取代多个出队命令，减少了离开和重新进入中断处理程序的开销。对于没有待复位的待处理中断指示符的情况，保留一个否定的响应。

2. 发明申请

US20080320216A1 Translation Lookaside Buffer and Related Method and Program Product Utilized For Virtual Addresses 失效
标题翻译：用于虚拟地址的翻译后备缓冲区和相关方法和程序产品
公开(公告)号：US20080320216A1
公开(公告)日：2008-12-25
申请号：US12142885
申请日：2008-06-20
申请人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
发明人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
IPC分类号： G06F12/00
CPC分类号： G06F12/1036
摘要： A program product, a translation lookaside buffer and a related method for operating the TLB is provided. The method comprises the steps of: a) when adding an entry for a virtual address to said TLB testing whether the attribute data of said virtual address is already stored in said CAM and if the attribute data is not stored already in said CAM, generating tag data for said virtual address such that said tag data is different from the tag data generated for the other virtual addresses currently stored in said RAM and associated to the new entry in said CAM for the attribute data, adding the generated tag data to said RAM and to the associated entry in said CAM, and setting a validity flag in said CAM for said associated entry; else if the attribute data is stored already in said CAM, adding the stored attribute data to the entry in said RAM for said virtual address; and when performing a TLB lookup operation: reading the validity flag and the tag data from the entry in said CAM, which is associated to the entry in said RAM for said virtual address, and simultaneously reading the absolute address and the tag data from the entry in said RAM for said virtual address, and generating a TLB hit only if the tag data read from said CAM is valid and matches the tag data read from said RAM.
摘要翻译：提供了一种程序产品，翻译后备缓冲器和用于操作TLB的相关方法。该方法包括以下步骤：a）当向所述TLB添加虚拟地址的条目时，测试所述虚拟地址的属性数据是否已经存储在所述CAM中，并且属性数据是否已经存储在所述CAM中，生成标签用于所述虚拟地址的数据，使得所述标签数据不同于当前存储在所述RAM中并与所述CAM中的新条目相关联的用于属性数据的其他虚拟地址生成的标签数据，将生成的标签数据添加到所述RAM，到所述CAM中的相关联的条目，并且在所述CAM中为所述相关联的条目设置有效标志; 否则如果属性数据已经存储在所述CAM中，则将存储的属性数据添加到用于所述虚拟地址的所述RAM中的条目; 并且当执行TLB查找操作时：从与所述RAM中的所述虚拟地址的条目相关联的所述CAM中的条目读取有效性标志和标签数据，并同时从所述条目读取绝对地址和标签数据在所述RAM中用于所述虚拟地址，并且仅当从所述CAM读取的标签数据有效并且与从所述RAM读取的标签数据匹配时才产生TLB命中。

3. 发明授权

US08572624B2 Providing multiple quiesce state machines in a computing environment 有权
标题翻译：在计算环境中提供多个静默状态机
公开(公告)号：US08572624B2
公开(公告)日：2013-10-29
申请号：US12037734
申请日：2008-02-26
申请人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
发明人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
IPC分类号： G06F9/46 , G06F7/38
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.
摘要翻译：一种用于提供多个静默状态机的系统，方法和计算机程序产品。该系统包括第一控制器，其包括用于处理第一静默请求的逻辑。该系统还包括第二控制器，其包括用于处理第二静默请求的逻辑。处理第二停顿请求的全部或一部分与处理第一停顿请求的时间重叠。因此，多个静默请求可能在系统中同时处于活动状态。

4. 发明授权

US08166239B2 Translation lookaside buffer and related method and program product utilized for virtual addresses 失效
标题翻译：翻译后备缓冲区以及用于虚拟地址的相关方法和程序产品
公开(公告)号：US08166239B2
公开(公告)日：2012-04-24
申请号：US12142885
申请日：2008-06-20
申请人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
发明人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1036
摘要： A program product, a translation lookaside buffer and a related method for operating the TLB is provided. The method comprises the steps of: a) when adding an entry for a virtual address to said TLB testing whether the attribute data of said virtual address is already stored in said CAM and if the attribute data is not stored already in said CAM, generating tag data for said virtual address such that said tag data is different from the tag data generated for the other virtual addresses currently stored in said RAM and associated to the new entry in said CAM for the attribute data, adding the generated tag data to said RAM and to the associated entry in said CAM, and setting a validity flag in said CAM for said associated entry; else if the attribute data is stored already in said CAM, adding the stored attribute data to the entry in said RAM for said virtual address; and when performing a TLB lookup operation: reading the validity flag and the tag data from the entry in said CAM, which is associated to the entry in said RAM for said virtual address, and simultaneously reading the absolute address and the tag data from the entry in said RAM for said virtual address, and generating a TLB hit only if the tag data read from said CAM is valid and matches the tag data read from said RAM.
摘要翻译：提供了一种程序产品，翻译后备缓冲器和用于操作TLB的相关方法。该方法包括以下步骤：a）当向所述TLB添加虚拟地址的条目时，测试所述虚拟地址的属性数据是否已经存储在所述CAM中，并且属性数据是否已经存储在所述CAM中，生成标签用于所述虚拟地址的数据，使得所述标签数据不同于当前存储在所述RAM中并与所述CAM中的新条目相关联的用于属性数据的其他虚拟地址生成的标签数据，将生成的标签数据添加到所述RAM，到所述CAM中的相关联的条目，并且在所述CAM中为所述相关联的条目设置有效标志; 否则如果属性数据已经存储在所述CAM中，则将存储的属性数据添加到用于所述虚拟地址的所述RAM中的条目; 并且当执行TLB查找操作时：从与所述RAM中的所述虚拟地址的条目相关联的所述CAM中的条目读取有效性标志和标签数据，并同时从所述条目读取绝对地址和标签数据在所述RAM中用于所述虚拟地址，并且仅当从所述CAM读取的标签数据有效并且与从所述RAM读取的标签数据匹配时才产生TLB命中。

5. 发明授权

US08850129B2 Memory ordered store system in a multiprocessor computer system 有权
标题翻译：内存订购存储系统在多处理器计算机系统中
公开(公告)号：US08850129B2
公开(公告)日：2014-09-30
申请号：US12822331
申请日：2010-06-24
申请人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
发明人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
IPC分类号： G06F12/02 , G06F12/08 , G06F9/38 , G06F12/10 , G06F9/52
CPC分类号： G06F12/0815 , G06F9/3842 , G06F9/528 , G06F12/0828 , G06F12/0831 , G06F12/0862 , G06F12/1054 , G06F2212/1016 , G06F2212/507 , G06F2212/621
摘要： A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.
摘要翻译：提供了一种用于以快速的顺序将数据存储在计算机系统的存储器中的系统和计算机实现的方法。该方法包括向存储器启动第一个存储。启动等待计数器。当等待计数器到期时，第二家存储器被推测启动。当第二个存储在第一个存储到存储器之前实现相关性时，第二个存储器的存储被取消。

6. 发明申请

US20130166803A1 DEQUEUE OPERATION USING MASK VECTOR TO MANAGE INPUT/OUTPUT INTERRUPTIONS 失效
标题翻译：使用掩码向量来管理输入/输出中断的DEQUEUE操作
公开(公告)号：US20130166803A1
公开(公告)日：2013-06-27
申请号：US13332427
申请日：2011-12-21
申请人： Janet R. Easton , Norbert Hagspiel , Bernd Nerz
发明人： Janet R. Easton , Norbert Hagspiel , Bernd Nerz
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.
摘要翻译：发出命令以重置一个或多个待处理的中断指示符并仲裁中断的所有权。响应于接收到该命令的处理器，检查所选待处理的中断指示符。如果未设置所选待处理的中断指示符，则会检查另一个未决中断指示符，而不是提供否定响应并重新发出命令。以这种方式，一个出队命令可以取代多个出队命令，减少了离开和重新进入中断处理程序的开销。对于没有待复位的待处理中断指示符的情况，保留一个否定的响应。

7. 发明申请

US20090217269A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING MULTIPLE QUIESCE STATE MACHINES 有权
标题翻译：用于提供多种状态机器的系统，方法和计算机程序产品
公开(公告)号：US20090217269A1
公开(公告)日：2009-08-27
申请号：US12037734
申请日：2008-02-26
申请人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
发明人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
IPC分类号： G06F9/46
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.
摘要翻译：一种用于提供多个静默状态机的系统，方法和计算机程序产品。该系统包括第一控制器，其包括用于处理第一静默请求的逻辑。该系统还包括第二控制器，其包括用于处理第二静默请求的逻辑。处理第二停顿请求的全部或一部分与处理第一停顿请求的时间重叠。因此，多个静默请求可能在系统中同时处于活动状态。

8. 发明申请

US20060179233A1 Method, system, and computer program product for implementing a dual-addressable cache 失效
标题翻译：用于实现双重寻址缓存的方法，系统和计算机程序产品
公开(公告)号：US20060179233A1
公开(公告)日：2006-08-10
申请号：US11054298
申请日：2005-02-09
申请人： Norbert Hagspiel , Erwin Pfeffer , Bruce Wagar
发明人： Norbert Hagspiel , Erwin Pfeffer , Bruce Wagar
IPC分类号： G06F12/00
CPC分类号： G06F12/0864
摘要： A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.
摘要翻译：提供了一种用于实现双重寻址缓存的方法，系统和计算机程序产品。该方法包括为缓存目录中提供的每个同余类添加间接索引的字段。缓存目录由主地址索引。响应于基于对应于主地址的已知辅助地址的主地址的请求，该方法还包括生成辅助地址的索引，以及将间接索引中的一个插入或更新到一个字段中以用于一致与次要地址相关的课程。为间接索引分配与主地址相对应的虚拟索引的值。该方法还包括搜索辅助地址的每个间接索引的同余类。

9. 发明授权

US06654669B2 Processor unit for a data-processing-aided electronic control system in a motor vehicle 失效
标题翻译：用于机动车辆中的数据处理辅助电子控制系统的处理器单元
公开(公告)号：US06654669B2
公开(公告)日：2003-11-25
申请号：US09192215
申请日：1998-11-16
申请人： Joachim Eisenmann , Stefan Gleissner , Philipp Lanches , Markus Mrossko , Hans-Juergen Aminger , Wolfgang Eibach , Volkmar Goetze , Matthias Gruetzner , Norbert Hagspiel , Matthias Koehn , Martin Neumann , Reiner Rieke , Dieter Staiger
发明人： Joachim Eisenmann , Stefan Gleissner , Philipp Lanches , Markus Mrossko , Hans-Juergen Aminger , Wolfgang Eibach , Volkmar Goetze , Matthias Gruetzner , Norbert Hagspiel , Matthias Koehn , Martin Neumann , Reiner Rieke , Dieter Staiger
IPC分类号： G01M1700
CPC分类号： G06F15/7864 , G06F9/3877
摘要： A processor unit for a data-processing-aided electronic control system in a motor vehicle, in which the processor unit operates in real-time and contains within its functional structure a scalable computing unit and a vehicle interface unit, as well as (preferably) a communication coprocessor as separate structural components.
摘要翻译：一种用于机动车辆中的数据处理辅助电子控制系统的处理器单元，其中处理器单元实时操作并且在其功能结构内包含可扩展计算单元和车辆接口单元，以及（优选地）通信协处理器作为单独的结构组件。

10. 发明申请

US20110320743A1 MEMORY ORDERED STORE SYSTEM IN A MULTIPROCESSOR COMPUTER SYSTEM 有权
标题翻译：多处理器计算机系统中的存储订单存储系统
公开(公告)号：US20110320743A1
公开(公告)日：2011-12-29
申请号：US12822331
申请日：2010-06-24
申请人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
发明人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F9/3842 , G06F9/528 , G06F12/0828 , G06F12/0831 , G06F12/0862 , G06F12/1054 , G06F2212/1016 , G06F2212/507 , G06F2212/621
摘要： A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.
摘要翻译：提供了一种用于以快速的顺序将数据存储在计算机系统的存储器中的系统和计算机实现的方法。该方法包括向存储器启动第一个存储。启动等待计数器。当等待计数器到期时，第二家存储器被推测启动。当第二个存储在第一个存储到存储器之前实现相关性时，第二个存储器的存储被取消。

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