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    • 1. 发明授权
      US6078218A Negative amplifier circuit 失效
    • Negative amplifier circuit
    • 负放大电路
    • US6078218A
    • 2000-06-20
    • US33109
    • 1998-03-02
    • Atsushi Hirabayashi , Kosuke Fujita , Kenji Komori , Norihiro Murayama
    • Atsushi Hirabayashi , Kosuke Fujita , Kenji Komori , Norihiro Murayama
    • H03G3/10 , H03F3/45 , H03G1/00 , H23G3/32
    • H03G1/0023 , H03F2200/87 , H03F2203/45468 , H03F2203/45471
    • An amplifier circuit in which a differential pair of transistors (1a), (1b) is provided. An impedance (2) of a value 2.Z.sub.e is connected in series between the emitters of the transistors (1a), (1b) and these emitters are grounded by way of current sources (3a), (3b) respectively. Input signal sources (4a), (4b) of voltage values.+-.V.sub.IN are connected to the bases of the transistors (1a), (1b) by way of the base-emitter paths of the transistors (5a), (5b) which form a buffer circuit (10). The emitters of the transistors (5a), (5b) are in turn grounded by way of current sources (6a), (6b) respectively. Further, the collectors of each of the transistors (1a), (1b) are connected to the base of the other transistors by way of the base-emitter paths of the transistors (5a), (5b) respectively.
    • 一种放大器电路，其中提供了差分对晶体管（1a），（1b）。 （2）的阻抗（2）串联连接在晶体管（1a），（1b）的发射极之间，这些发射极分别通过电流源（3a），（3b）接地。 电压值+/- VIN的输入信号源（4a），（4b）通过晶体管（5a），（5b）的基极 - 发射极连接到晶体管（1a），（1b）的基极， 形成缓冲电路（10）。 晶体管（5a），（5b）的发射极分别通过电流源（6a），（6b）接地。 此外，晶体管（1a），（1b）中的每一个的集电极分别通过晶体管（5a），（5b）的基极 - 发射极连接到其它晶体管的基极。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US6051965A Two-terminal paired circuit 失效
    • Two-terminal paired circuit
    • 双端配对电路
    • US6051965A
    • 2000-04-18
    • US170097
    • 1998-10-13
    • Atsushi Hirabayashi , Kosuke Fujita , Kenji Komori , Norihiro Murayama
    • Atsushi Hirabayashi , Kosuke Fujita , Kenji Komori , Norihiro Murayama
    • H03F1/56 , H03H11/46 , G05F3/04 , H03F3/26 , H03K1/14
    • H03H11/46 , H03F1/56
    • A two-terminal paired circuit is disclosed which comprises two sets of differential pairs wherein a first set of the differential pair includes two transistors collectors of which are connected to a pair of input terminals and to a bias circuit serving also as a DC shift, bases of which are connected to the bias circuit to apply a voltage feedback from the collectors to the bases and emitters of which are connected to a constant current source and have an impedance element connected therebetween, a second set of the differential pair includes two transistors collectors of which are connected to a pair of output terminals and to a bias circuit serving also as a DC shift, bases of which are connected to the bias circuit to apply a voltage feedback from the collectors to the bases and emitters of which are connected to a constant current source and have an impedance element connected therebetween, and the voltage feedbacks together with the two sets of differential pairs are applied symmetrical with respect to left and right, whereby the impedances connected between the emitters exist in series between the input and output terminals.
    • 公开了一种双端子配对电路，其包括两组差分对，其中差分对的第一组包括两个晶体管集电极，其连接到一对输入端子以及还用作DC移位的偏置电路，基极 其连接到偏置电路以将来自集电极的电压反馈施加到其基极和发射极连接到恒流源并且在其之间连接有阻抗元件，第二组差分对包括两个晶体管集电极 其连接到一对输出端子以及还用作DC偏移的偏置电路，其基极连接到偏置电路以将来自集电极的电压反馈施加到其基极和发射极连接到恒定电压 电流源并且在其间连接阻抗元件，并且与两组差分对一起施加电压反馈 相对于左右的三角形，由此连接在发射器之间的阻抗串联在输入端和输出端之间。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US06396354B1 PLL detection circuit with lock judgement circuit 失效
    • PLL detection circuit with lock judgement circuit
    • PLL锁定判断电路检测电路
    • US06396354B1
    • 2002-05-28
    • US09621842
    • 2000-07-24
    • Norihiro Murayama , Kosuke Fujita
    • Norihiro Murayama , Kosuke Fujita
    • H03L7095
    • H04N5/50 , H03D1/2281 , H04N5/455 , H04N21/426 , H04N21/4382 , Y10S331/02
    • Phase locked loop (PLL) detection circuit that can improve the stability of operation, avoid occurrence of an erroneous operation, and perform PLL lock judgment correctly. Whether a PLL circuit that consists of a phase comparator, a low-pass filter, and a VCO is in a lock state is judged based on a phase error signal in the PLL circuit. The level of the phase error signal is compared with two threshold values, VRL and VRH. When the phase error signal is somewhere between VRL and VRH, a judgment is made that the PLL circuit is in a lock state. A judgment that the PLL circuit is out of a lock state is made in the other cases. This makes it possible to output a correct and stable PLL lock judgment signal.
    • 锁相环（PLL）检测电路，可以提高操作的稳定性，避免发生错误的操作，并正确执行PLL锁定判断。 基于PLL电路中的相位误差信号来判断由相位比较器，低通滤波器和VCO组成的PLL电路处于锁定状态。 将相位误差信号的电平与两个阈值VRL和VRH进行比较。 当相位误差信号在VRL和VRH之间时，判断为PLL电路处于锁定状态。 在其他情况下，判定为PLL电路处于锁定状态。 这使得可以输出正确和稳定的PLL锁定判断信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US06292032B1 High impedance circuit 失效
    • High impedance circuit
    • 高阻抗电路
    • US06292032B1
    • 2001-09-18
    • US09570561
    • 2000-05-12
    • Atsushi Hirabayashi , Kosuke Fujita , Kenji Komori , Norihiro Murayama
    • Atsushi Hirabayashi , Kosuke Fujita , Kenji Komori , Norihiro Murayama
    • H03K500
    • H03F1/56 , H03H11/28
    • A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector resistance elements, a resistance element and a pair of current source circuits. The third and the fourth transistors serve as emitter follower circuits which also functions as a DC shift with respect to the differential-pair type circuit, as well as buffer circuits for heightening an input impedance of the first and the second transistors looked from the base side of the third and the fourth transistors. The current flowing in the resistance element is made current-fedback with respect to the resistance elements by the third and the fourth transistors. The input impedance is determined as Z1=V1/ i3=(R1×R2)/(R1−R2), and when R1=R2, the high impedance circuit becomes infinite impedance.
    • 提供了能够在低电压下工作而不使动态范围变窄的高阻抗电路，其包括形成差分对型电路的第一和第二晶体管，第三和第四晶体管，一对集电极电阻元件，电阻元件 和一对电流源电路。 第三和第四晶体管用作射极跟随器电路，其也用作相对于差分对型电路的DC偏移，以及缓冲电路，用于提高从基极侧看的第一和第二晶体管的输入阻抗 的第三和第四晶体管。 流过电阻元件的电流通过第三和第四晶体管相对于电阻元件进行电流反馈。 输入阻抗确定为Z1 = V1 / i3 =（R1xR2）/（R1-R2），当R1 = R2时，高阻抗电路变为无限阻抗。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US6133763A High impedance circuit 失效
    • High impedance circuit
    • 高阻抗电路
    • US6133763A
    • 2000-10-17
    • US154096
    • 1998-09-16
    • Atsushi Hirabayashi , Kosuke Fujita , Kenji Komori , Norihiro Murayama
    • Atsushi Hirabayashi , Kosuke Fujita , Kenji Komori , Norihiro Murayama
    • H03F1/56 , H03H11/28 , H03H11/46 , H03K5/153
    • H03F1/56 , H03H11/28
    • A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector resistance elements, a resistance element and a pair of current source circuits. The third and the fourth transistors serve as emitter follower circuits which also functions as a DC shift with respect to the differential-pair type circuit, as well as buffer circuits for heightening an input impedance of the first and the second transistors looked from the base side of the third and the fourth transistors. The current flowing in the resistance element is made current-fedback with respect to the resistance elements by the third and the fourth transistors. The input impedance is determined as Z1=V1/i3=(R1.times.R2)/(R1-R2), and when R1=R2, the high impedance circuit becomes infinite impedance.
    • 提供了能够在低电压下工作而不使动态范围变窄的高阻抗电路，其包括形成差分对型电路的第一和第二晶体管，第三和第四晶体管，一对集电极电阻元件，电阻元件 和一对电流源电路。 第三和第四晶体管用作射极跟随器电路，其也用作相对于差分对型电路的DC偏移，以及缓冲电路，用于提高从基极侧看的第一和第二晶体管的输入阻抗 的第三和第四晶体管。 流过电阻元件的电流通过第三和第四晶体管相对于电阻元件进行电流反馈。 输入阻抗确定为Z1 = V1 / i3 =（R1xR2）/（R1-R2），当R1 = R2时，高阻抗电路变为无限阻抗。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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