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1. 发明授权

US09727464B2 Nested cache coherency protocol in a tiered multi-node computer system 有权
公开(公告)号：US09727464B2
公开(公告)日：2017-08-08
申请号：US14549429
申请日：2014-11-20
申请人： Garrett Michael Drapala , William J Lewis , Pak-kin Mak , Robert J Sonnelitter, III
发明人： Garrett Michael Drapala , William J Lewis , Pak-kin Mak , Robert J Sonnelitter, III
IPC分类号： G06F12/08 , G06F12/0815 , G06F12/0817 , G06F12/0806
CPC分类号： G06F12/0824 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F2212/60 , G06F2212/621
摘要： A computer system comprising multiple nodes, each node comprising a plurality of processors and a local cache hierarchy, suppresses local cache coherency of a node operations or global cache coherency operations between nodes based on the coherency request being a global or local request, and the state of the cache line at the node.

2. 发明申请

US20160147659A1 NESTED CACHE COHERENCY PROTOCOL IN A TIERED MULTI-NODE COMPUTER SYSTEM 有权
公开(公告)号：US20160147659A1
公开(公告)日：2016-05-26
申请号：US14549429
申请日：2014-11-20
申请人： Garrett Michael Drapala , William J Lewis , Pak-kin Mak , Robert J Sonnelitter, III
发明人： Garrett Michael Drapala , William J Lewis , Pak-kin Mak , Robert J Sonnelitter, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0824 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F2212/60 , G06F2212/621
摘要： A computer system comprising multiple nodes, each node comprising a plurality of processors and a local cache hierarchy, suppresses local cache coherency of a node operations or global cache coherency operations between nodes based on the coherency request being a global or local request, and the state of the cache line at the node.

3. 发明授权

US08918587B2 Multilevel cache hierarchy for finding a cache line on a remote node 有权
标题翻译：用于在远程节点上查找缓存行的多级缓存层次结构
公开(公告)号：US08918587B2
公开(公告)日：2014-12-23
申请号：US13495373
申请日：2012-06-13
申请人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
发明人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0884 , G06F12/123
摘要： Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
摘要翻译：实施例涉及在具有系统存储器的多级缓存系统上访问高速缓存行。基于本地节点对特定高速缓存线的独占所有权的请求，请求被本地节点同时发送到用于特定高速缓存行的多个节点的系统内存和远程节点。在特定的远程节点中找到特定的高速缓存行。特定的远程节点是远程节点之一。从特定的远程节点中删除特定的高速缓存行以供另一个节点独占所有。基于具有指定缓存行在幽灵状态的指定节点，任何后续的提取请求将针对具体的缓存行启动，特定的缓存行遇到幽灵状态。当遇到鬼状态时，后续的提取请求仅被引导到多个节点的节点。

4. 发明授权

US08656228B2 Memory error isolation and recovery in a multiprocessor computer system 有权
标题翻译：多处理器计算机系统中的内存错误隔离和恢复
公开(公告)号：US08656228B2
公开(公告)日：2014-02-18
申请号：US12821271
申请日：2010-06-23
申请人： Mark A. Check , David F. Craddock , Thomas A. Gregg , Pak-kin Mak , Gary E. Strait
发明人： Mark A. Check , David F. Craddock , Thomas A. Gregg , Pak-kin Mak , Gary E. Strait
IPC分类号： G06F11/00
CPC分类号： G06F11/0745 , G06F11/0724 , G06F11/0793 , G06F12/1458
摘要： A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.
摘要翻译：提供了一种用于隔离计算机系统中的错误的系统和计算机实现的方法。该方法包括接收访问计算机存储器的直接存储器访问（DMA）命令，读取响应或中断; 将DMA命令与由流标识（ID）标识的流相关联以访问计算机存储器，读取响应或中断; 检测由流中的DMA命令引起的存储器错误，存储器错误导致计算机存储器中的过时数据; 并且在检测到存储器错误时，将与流ID相关联的流中的存储器错误与其他流ID相关联的其他流隔离。

5. 发明授权

US08560776B2 Method for expediting return of line exclusivity to a given processor in a symmetric multiprocessing data processing system 失效
标题翻译：在对称多处理数据处理系统中加速线路排他性返回到给定处理器的方法
公开(公告)号：US08560776B2
公开(公告)日：2013-10-15
申请号：US12021403
申请日：2008-01-29
申请人： Garrett M. Drapala , Pak-kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Garrett M. Drapala , Pak-kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A method and apparatus for eliminating, in a multi-nodes data handling system, contention for exclusivity of lines in cache memory through improved management of system buses, processor cross-invalidate stacks, and the system operations that can lead to these requested cache operations being rejected.
摘要翻译：一种用于在多节点数据处理系统中消除通过改进的系统总线管理，处理器交叉无效堆栈以及可导致这些所请求的高速缓存操作的系统操作的高速缓冲存储器中线路排他性的争用的方法和装置拒绝。

6. 发明申请

US20110320755A1 TRACKING DYNAMIC MEMORY REALLOCATION USING A SINGLE STORAGE ADDRESS CONFIGURATION TABLE 失效
标题翻译：使用单个存储地址配置表跟踪动态内存重新安装
公开(公告)号：US20110320755A1
公开(公告)日：2011-12-29
申请号：US12821986
申请日：2010-06-23
申请人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
发明人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
IPC分类号： G06F12/06
CPC分类号： G06F12/0292
摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.
摘要翻译：使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个注册到第一个寄存器，使用单个配置表完成内存取消分配。

7. 发明申请

US20110314228A1 Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer 失效
标题翻译：维持多节点对称多处理计算机中的缓存一致性
公开(公告)号：US20110314228A1
公开(公告)日：2011-12-22
申请号：US12816464
申请日：2010-06-16
申请人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0833
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译：在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

8. 发明授权

US07634708B2 Relocatable storage protect keys for system main memory 有权
标题翻译：系统主存储器的可重定位存储保护键
公开(公告)号：US07634708B2
公开(公告)日：2009-12-15
申请号：US11532294
申请日：2006-09-15
申请人： Kevin W. Kark , Liyong Wang , Carl B. Ford, III , Pak-kin Mak
发明人： Kevin W. Kark , Liyong Wang , Carl B. Ford, III , Pak-kin Mak
IPC分类号： G06F11/00
CPC分类号： G06F12/1475 , G06F11/08
摘要： Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-detect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.
摘要翻译：存储保护密钥和系统数据共享相同的物理存储。关键区域是通过固件动态重新定位。配置阵列用于将关键区域的绝对地址映射到其物理地址。即使键的物理位置被重新定位到不同的区域，键的绝对地址也可以被固定。三重检测双正确ECC方案用于保护密钥。 ECC方案与存储中的常规数据不同，可用于检测非法访问。额外的固件和硬件也旨在限制客户的应用程序直接访问密钥。在可重新定位关键区域的情况下，固件可以将密钥区域从存储器中的已知故障区域移开，以改善系统RAS。我们还实现了共同目标，即密钥存储设备可以与不使用密钥的其他服务器系统使用相同的存储设备。

9. 发明申请

US20090210629A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SELECTIVELY PURGING CACHE ENTRIES 审中-公开
标题翻译：方法，系统和计算机程序产品，用于选择高速缓存进入
公开(公告)号：US20090210629A1
公开(公告)日：2009-08-20
申请号：US12032058
申请日：2008-02-15
申请人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
发明人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.
摘要翻译：一种用于选择性地清除计算机系统的高速缓存中的条目的方法，系统和计算机程序产品。该方法包括确定要清除的存储地址范围的起始存储地址和长度，确定高速缓存目录的同余类和隔间的预设值，基于同余类的预设值访问高速缓存目录;以及基于所述隔室的所述预设值来选择所述缓存目录中的条目，通过检查所述条目的所有权标签来确定所访问的条目的有效性，将所述条目的行地址与所述起始存储地址进行比较，以及所述起始存储器地址和存储地址范围的长度，并且基于比较结果选择性地清除条目。

10. 发明授权

US07577795B2 Disowning cache entries on aging out of the entry 失效
标题翻译：在条目中老化的缓存条目不起作用
公开(公告)号：US07577795B2
公开(公告)日：2009-08-18
申请号：US11339196
申请日：2006-01-25
申请人： David S. Hutton , Kathryn M. Jackson , Keith N. Langston , Pak-kin Mak , Chung-Lung K. Shum
发明人： David S. Hutton , Kathryn M. Jackson , Keith N. Langston , Pak-kin Mak , Chung-Lung K. Shum
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0811 , G06F12/12
摘要： Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the main memory. For a system with shared L2 cache(s) between the processor(s) and the main memory, an individual L1 cache of a processor must first communicate to an associated L2 cache(s), or check with such L2 cache(s), to obtain a copy of a particular line from a given cache location prior to, or upon modification, or appropriation of data at a given cached location. The individual L1 cache further includes provisions for notifying the L2 cache(s) upon determining when the data stored in the particular cache line in the L1 cache has been replaced, and when the particular cache line is disowned by an L1 cache, the L2 cache is updated to change the state of the particular cache line therein from an ownership state of exclusive to a particular identified CPU to an ownership state of exclusive to no CPU, thereby allowing reduction of cross interrogate delays during another processor acquisition of the same cache line.
摘要翻译：处理器系统中的数据部分存储在较慢的主存储器中，并被传送到包括一个或多个处理器与主存储器之间的高速缓存结构层级的更快的存储器。对于在处理器和主存储器之间具有共享L2高速缓存的系统，处理器的单个L1高速缓存必须首先通信到相关联的L2高速缓存，或者与这样的L2高速缓存进行检查，在给定的高速缓存位置之前或之后，在给定的高速缓存位置处获取特定行的副本，或者在修改之后获得数据的占用。单独的L1高速缓存还包括用于在确定何时存储在L1高速缓存中的特定高速缓存行中的数据已经被替换的情况下通知L2高速缓存，并且当特定高速缓存行被L1高速缓存取消时，L2高速缓存被更新为将其中的特定高速缓存行的状态从独占的所有权状态改变为特定的所识别的CPU到不属于CPU的独占的所有权状态，从而允许在对同一高速缓存行的另一个处理器采集期间减少交叉询问延迟。

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