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1. 发明授权

US08987104B2 Method of forming spacers that provide enhanced protection for gate electrode structures 有权
标题翻译：形成对栅电极结构提供增强保护的间隔物的方法
公开(公告)号：US08987104B2
公开(公告)日：2015-03-24
申请号：US13108363
申请日：2011-05-16
申请人： Peter Baars , Sven Beyer , Jan Hoentschel , Thilo Scheiper
发明人： Peter Baars , Sven Beyer , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763 , H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/78618 , H01L29/78687
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括在半导体衬底之上形成栅电极结构并在栅电极结构附近形成多个间隔区，其中多个间隔物包括邻近栅电极结构的侧壁定位的第一氮化硅间隔区，位于第一氮化硅间隔物附近的通常为L形的氮化硅间隔物，和位于大致L形的氮化硅间隔物附近的二氧化硅隔离物。

2. 发明授权

US08946821B2 SRAM integrated circuits and methods for their fabrication 有权
标题翻译： SRAM集成电路及其制造方法
公开(公告)号：US08946821B2
公开(公告)日：2015-02-03
申请号：US13348142
申请日：2012-01-11
申请人： Matthias Goldbach , Peter Baars
发明人： Matthias Goldbach , Peter Baars
IPC分类号： H01L27/12 , H01L27/11 , H01L27/02
CPC分类号： H01L27/1104 , H01L27/0207
摘要： SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.
摘要翻译：提供SRAM集成电路，其具有在硅衬底中及其上制造的SRAM单元的上拉和下拉晶体管。一层绝缘材料覆盖上拉和下拉晶体管。 SRAM单元的栅极晶体管制造在覆盖绝缘材料层的半导体层中。

3. 发明授权

US08883586B2 Mol insitu Pt rework sequence 有权
标题翻译：莫尔实验Pt返修序列
公开(公告)号：US08883586B2
公开(公告)日：2014-11-11
申请号：US13079492
申请日：2011-04-04
申请人： Peter Baars , Marco Lepper , Uwe Kahler , Vivien Schroeder
发明人： Peter Baars , Marco Lepper , Uwe Kahler , Vivien Schroeder
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3213 , H01L21/285 , H01L29/66 , H01L29/78 , H01L21/02
CPC分类号： H01L21/2855 , H01L21/02068 , H01L21/28518 , H01L21/32134 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.
摘要翻译：在形成含Pt的NiSi之后剩余的Pt残余物的量通过在形成浇口间隔件的同时进行O2闪光，然后清洗并应用Aqua Regia的第二次应用来减少。实施例包括在半导体衬底上溅射沉积Ni / Pt层，退火Ni / Pt层，湿剥离未反应的Ni，退火Ni剥离的Ni / Pt层，从退火的Ni / Pt层剥离未反应的Pt，例如， Aqua Regia，用氧等离子体处理Pt剥离的Ni / Pt层，清洁Ni / Pt层，以及从清洁的Ni / Pt层剥离未反应的Pt，例如，通过第二次应用Aqua Regia。

4. 发明授权

US08614123B2 Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures 有权
标题翻译：通过使用牺牲栅电极和牺牲自对准接触结构形成半导体器件的方法
公开(公告)号：US08614123B2
公开(公告)日：2013-12-24
申请号：US13305131
申请日：2011-11-28
申请人： Andy Wei , Peter Baars , Erik Geiss
发明人： Andy Wei , Peter Baars , Erik Geiss
IPC分类号： H01L21/8238
CPC分类号： H01L21/28079 , H01L21/76897 , H01L29/495 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.
摘要翻译：本文公开了使用牺牲栅电极和牺牲自对准触点形成半导体器件的各种方法。在一个示例中，该方法包括形成由第一材料构成的两个间隔开的牺牲栅电极，形成包括第二材料的牺牲接触结构，其中第二材料相对于所述第一材料可选择性地蚀刻，并且执行蚀刻在两个间隔开的牺牲栅电极和牺牲接触结构之间进行选择性地相对于牺牲接触结构选择性地去除两个间隔开的牺牲栅极电极结构。

5. 发明授权

US08592302B2 Patterning method for fabrication of a semiconductor device 有权
标题翻译：用于制造半导体器件的图案化方法
公开(公告)号：US08592302B2
公开(公告)日：2013-11-26
申请号：US13307079
申请日：2011-11-30
申请人： Erik P. Geiss , Peter Baars
发明人： Erik P. Geiss , Peter Baars
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/76816 , H01L21/76895 , H01L21/76897
摘要： A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.
摘要翻译：提供了一种用于制造具有导电接触元件的半导体器件结构，覆盖接触元件的层间绝缘材料，覆盖在层间电介质材料上的有机平坦化层，覆盖有机平坦化层的抗反射涂层材料和光刻胶材料的图案化方法覆盖抗反射涂层材料。该方法从光致抗蚀剂材料形成图案化的光致抗蚀剂层，以限定对应于各个导电接触元件的超大开孔。使用图案化的光致抗蚀剂作为蚀刻掩模蚀刻抗反射涂层。将衬垫材料沉积在图案化的抗反射涂层上。衬里材料被蚀刻以产生侧壁特征，其被用作蚀刻掩模的一部分以形成用于导电接触元件的接触凹部。

6. 发明授权

US08557666B2 Methods for fabricating integrated circuits 有权
公开(公告)号：US08557666B2
公开(公告)日：2013-10-15
申请号：US13231750
申请日：2011-09-13
申请人： Andy C. Wei , Peter Baars , Erik P. Geiss
发明人： Andy C. Wei , Peter Baars , Erik P. Geiss
IPC分类号： H01L21/336
CPC分类号： H01L21/823418 , H01L21/76224 , H01L21/76897 , H01L21/823431 , H01L21/823821 , H01L29/41783 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

7. 发明授权

US08513083B2 Methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes 有权
标题翻译：通过进行角度离子注入工艺形成衬底二极管的阳极和阴极的方法
公开(公告)号：US08513083B2
公开(公告)日：2013-08-20
申请号：US13218589
申请日：2011-08-26
申请人： Peter Baars , Thilo Scheiper
发明人： Peter Baars , Thilo Scheiper
IPC分类号： H01L21/8222
CPC分类号： H01L29/8611 , H01L21/26586 , H01L21/266 , H01L21/822 , H01L21/84 , H01L27/0629 , H01L27/1207 , H01L27/127 , H01L29/66136
摘要： Disclosed herein are various methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes. In one example, the method includes performing a first angled ion implantation process to form a first doped region in a bulk layer of an SOI substrate for one of the anode or the diode and, after performing the first angled ion implantation process, performing a second angled ion implantation process to form a second doped region in the bulk layer of the SOI substrate for the other of the anode and the diode, wherein said first and second angled ion implantation process are performed through the same masking layer.
摘要翻译：本文公开了通过进行角度离子注入工艺来形成衬底二极管的阳极和阴极的各种方法。在一个示例中，该方法包括执行第一成角度离子注入工艺以在用于阳极或二极管之一的SOI衬底的体层中形成第一掺杂区域，并且在执行第一成角度离子注入工艺之后，执行第二角度离子注入工艺，以在SOI衬底的体层中形成用于阳极和二极管中的另一个的第二掺杂区域，其中所述第一和第二成角度离子注入工艺通过相同的掩模层进行。

8. 发明申请

US20130175627A1 SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION 有权
标题翻译： SRAM集成电路及其制造方法
公开(公告)号：US20130175627A1
公开(公告)日：2013-07-11
申请号：US13348142
申请日：2012-01-11
申请人： Matthias Goldbach , Peter Baars
发明人： Matthias Goldbach , Peter Baars
IPC分类号： H01L27/12 , H01L21/768
CPC分类号： H01L27/1104 , H01L27/0207
摘要： SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.
摘要翻译：提供SRAM集成电路，其具有在硅衬底中及其上制造的SRAM单元的上拉和下拉晶体管。一层绝缘材料覆盖上拉和下拉晶体管。 SRAM单元的栅极晶体管制造在覆盖绝缘材料层的半导体层中。

9. 发明授权

US08399352B2 Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions 有权
标题翻译：半导体器件包括自对准接触棒和具有增加的通过着陆区域的金属线
公开(公告)号：US08399352B2
公开(公告)日：2013-03-19
申请号：US13331606
申请日：2011-12-20
申请人： Thomas Werner , Peter Baars , Frank Feustel
发明人： Thomas Werner , Peter Baars , Frank Feustel
IPC分类号： H01L21/4763
CPC分类号： H01L23/5384 , H01L21/76808 , H01L21/76813 , H01L21/76816 , H01L23/5226 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： When forming metal lines of the metal zero level, a reduced bottom width and an increased top width may be achieved by using appropriate patterning regimes, for instance using a spacer structure after forming an upper trench portion with a top width, or forming the lower portion of the trenches and subsequently applying a further mask and etch regime in which the top width is implemented. In this manner, metal lines connecting to self-aligned contact bars may be provided so as to exhibit a bottom width of 20 nm and less, while the top width may allow reliable contact to any vias of the metallization system.
摘要翻译：当形成金属零电平的金属线时，可以通过使用适当的图案化方案来实现减小的底部宽度和增加的顶部宽度，例如在形成具有顶部宽度的上部沟槽部分之后使用间隔结构，或者形成下部并且随后应用进一步实现顶部宽度的掩模和蚀刻方案。以这种方式，可以提供连接到自对准接触棒的金属线，以便表现出20nm以下的底部宽度，而顶部宽度可以允许与金属化系统的任何通孔的可靠接触。

10. 发明申请

US20130065371A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS 有权
标题翻译：制作集成电路的方法
公开(公告)号：US20130065371A1
公开(公告)日：2013-03-14
申请号：US13231750
申请日：2011-09-13
申请人： Andy C. Wei , Peter Baars , Erik P. Geiss
发明人： Andy C. Wei , Peter Baars , Erik P. Geiss
IPC分类号： H01L21/336 , H01L21/762 , H01L21/20
CPC分类号： H01L21/823418 , H01L21/76224 , H01L21/76897 , H01L21/823431 , H01L21/823821 , H01L29/41783 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.
摘要翻译：提供了用于制造集成电路的方法。一种方法包括将多个沟槽蚀刻成硅衬底并用绝缘材料填充沟槽以描绘多个间隔开的硅片。外延生长一层未掺杂的硅以形成翅片的上部未掺杂区域。虚拟门结构形成为覆盖并横向于多个翅片，并且后填充材料填充在虚拟栅极结构之间。去除虚拟栅极结构以暴露一部分散热片，并且将高k电介质材料和确定栅极电极材料的功函数沉积在鳍片的该部分上。去除后填充材料以暴露第二部分，并且在第二部分上形成金属硅化物接触。然后，将导电触点形成到功函数确定材料和金属硅化物。

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