专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110145834A1 CODE EXECUTION UTILIZING SINGLE OR MULTIPLE THREADS 有权
标题翻译：使用单个或多个螺纹的代码执行
公开(公告)号：US20110145834A1
公开(公告)日：2011-06-16
申请号：US12634855
申请日：2009-12-10
申请人： Peter Carl Damron
发明人： Peter Carl Damron
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.
摘要翻译：使用主要硬件线程执行程序。在执行期间，指令指定执行使用工作人员硬件线程的部分。如果处理器状态指示器设置为多线程，则使用工作程序硬件线程执行指定的部分。然而，如果处理器状态指示器设置为单线程，则使用主硬件线程作为子例程来执行指定部分。主要硬件线程可以通过将主要硬件线程的参数数据寄存器或存储器位置复制到工作人员硬件线程的等效参数数据寄存器或存储器位置来将参数数据传递给工作者硬件线程。类似地，工作者硬件线程可以通过将用于工作者硬件线程的返回值寄存器或存储器位置复制到主硬件线程的等效返回值寄存器或存储器位置来将返回值传递给主要硬件线程。

2. 发明申请

US20110138372A1 REGISTER PRESPILL PHASE IN A COMPILER 有权
标题翻译：寄存器相关于编译器
公开(公告)号：US20110138372A1
公开(公告)日：2011-06-09
申请号：US12631256
申请日：2009-12-04
申请人： Peter Carl Damron
发明人： Peter Carl Damron
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： The present disclosure provides a compiler prespill phase that reduces or eliminates excessive register pressure, or locations in the code of a program where live virtual registers exceeds physical registers of a target computing device, prior to register allocation. The prespill phase identifies points of excessive register pressure, selects candidate virtual registers, chooses virtual registers to prespill from the candidates, and inserts spill and reload instructions to prespill the chosen registers. The prespill phase may reduce the register pressure such that the live virtual registers only exceed the physical registers by a particular number, the live virtual registers equal the physical registers, or the physical registers exceed the live virtual registers by a particular number. The compiler may then perform one or more early and/or late instruction scheduling phases, including global and/or local instruction scheduling, to optimize the placement of the spill and reload instructions.
摘要翻译：本公开提供了一种在注册分配之前减少或消除过多的注册压力或虚拟寄存器超过目标计算设备的物理寄存器的程序的代码中的位置的编译器预扩展阶段。预戳阶段标识过多寄存器压力的点，选择候选虚拟寄存器，选择虚拟寄存器从候选者预先插入，并插入溢出和重新加载指令来预先选择寄存器。预扩展阶段可以减小寄存器压力，使得虚拟寄存器仅通过特定数字超过物理寄存器，虚拟寄存器等于物理寄存器，或者物理寄存器通过特定数量超过实际虚拟寄存器。编译器然后可以执行一个或多个早期和/或延迟指令调度阶段，包括全局和/或本地指令调度，以优化溢出和重新加载指令的放置。

3. 发明授权

US08555034B2 Execution of variable width vector processing instructions 有权
标题翻译：执行可变宽度向量处理指令
公开(公告)号：US08555034B2
公开(公告)日：2013-10-08
申请号：US12638671
申请日：2009-12-15
申请人： Peter Carl Damron
发明人： Peter Carl Damron
IPC分类号： G06F17/16 , G06F9/302
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30076 , G06F9/30101 , G06F9/30189 , G06F9/3887
摘要： A processing unit executes a vector width instruction in a program and the processing unit obtains and supplies the width of an appropriate vector register that will be used to process variable vector processing instructions. Then, when the processing unit executes variable vector processing instructions in the program, the processing unit processes the variable vector processing instructions using the appropriate vector register with the instructions having the same width as the appropriate vector register. The width that the processing unit obtains may be less than an actual width of the appropriate vector register and may set by the processing unit. In this way, many different vector widths can be supported using a single set of instructions for vector processing. New instructions are not required if vector widths are changed and processing units having vector registers of differing widths do not require different code.
摘要翻译：处理单元在程序中执行向量宽度指令，并且处理单元获得并提供将用于处理可变向量处理指令的适当向量寄存器的宽度。然后，当处理单元在程序中执行可变向量处理指令时，处理单元使用具有与适当向量寄存器相同宽度的指令的适当向量寄存器处理可变向量处理指令。处理单元获得的宽度可以小于适当向量寄存器的实际宽度，并且可以由处理单元设置。以这种方式，可以使用一组用于向量处理的指令来支持许多不同的向量宽度。如果矢量宽度改变，并且具有不同宽度的矢量寄存器的处理单元不需要不同的代码，则不需要新的指令。

4. 发明授权

US08516465B2 Register prespill phase in a compiler 有权
标题翻译：在编译器中注册prepill阶段
公开(公告)号：US08516465B2
公开(公告)日：2013-08-20
申请号：US12631256
申请日：2009-12-04
申请人： Peter Carl Damron
发明人： Peter Carl Damron
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： The present disclosure provides a compiler prespill phase that reduces or eliminates excessive register pressure, or locations in the code of a program where live virtual registers exceeds physical registers of a target computing device, prior to register allocation. The prespill phase identifies points of excessive register pressure, selects candidate virtual registers, chooses virtual registers to prespill from the candidates, and inserts spill and reload instructions to prespill the chosen registers. The prespill phase may reduce the register pressure such that the live virtual registers only exceed the physical registers by a particular number, the live virtual registers equal the physical registers, or the physical registers exceed the live virtual registers by a particular number. The compiler may then perform one or more early and/or late instruction scheduling phases, including global and/or local instruction scheduling, to optimize the placement of the spill and reload instructions.
摘要翻译：本公开提供了一种在注册分配之前减少或消除过多的注册压力或虚拟寄存器超过目标计算设备的物理寄存器的程序的代码中的位置的编译器预扩展阶段。预戳阶段标识过多寄存器压力的点，选择候选虚拟寄存器，选择虚拟寄存器从候选者预先插入，并插入溢出和重新加载指令来预先选择寄存器。预扩展阶段可以减小寄存器压力，使得虚拟寄存器仅通过特定数字超过物理寄存器，虚拟寄存器等于物理寄存器，或者物理寄存器通过特定数量超过实际虚拟寄存器。编译器然后可以执行一个或多个早期和/或延迟指令调度阶段，包括全局和/或本地指令调度，以优化溢出和重新加载指令的放置。

5. 发明授权

US08612978B2 Code execution utilizing single or multiple threads 有权
标题翻译：使用单线程或多线程的代码执行
公开(公告)号：US08612978B2
公开(公告)日：2013-12-17
申请号：US12634855
申请日：2009-12-10
申请人： Peter Carl Damron
发明人： Peter Carl Damron
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.
摘要翻译：使用主要硬件线程执行程序。在执行期间，指令指定执行使用工作人员硬件线程的部分。如果处理器状态指示器设置为多线程，则使用工作程序硬件线程执行指定的部分。然而，如果处理器状态指示器设置为单线程，则使用主硬件线程作为子例程来执行指定部分。主要硬件线程可以通过将主要硬件线程的参数数据寄存器或存储器位置复制到工作人员硬件线程的等效参数数据寄存器或存储器位置来将参数数据传递给工作者硬件线程。类似地，工作者硬件线程可以通过将工作者硬件线程的返回值寄存器或存储器位置复制到主硬件线程的等效返回值寄存器或存储器位置来将返回值传递给主要硬件线程。

6. 发明申请

US20110145543A1 EXECUTION OF VARIABLE WIDTH VECTOR PROCESSING INSTRUCTIONS 有权
标题翻译：可变宽度矢量处理指令的执行
公开(公告)号：US20110145543A1
公开(公告)日：2011-06-16
申请号：US12638671
申请日：2009-12-15
申请人： Peter Carl Damron
发明人： Peter Carl Damron
IPC分类号： G06F9/30
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30076 , G06F9/30101 , G06F9/30189 , G06F9/3887
摘要： A processing unit executes a vector width instruction in a program and the processing unit obtains and supplies the width of an appropriate vector register that will be used to process variable vector processing instructions. Then, when the processing unit executes variable vector processing instructions in the program, the processing unit processes the variable vector processing instructions using the appropriate vector register with the instructions having the same width as the appropriate vector register. The width that the processing unit obtains may be less than an actual width of the appropriate vector register and may set by the processing unit. In this way, many different vector widths can be supported using a single set of instructions for vector processing. New instructions are not required if vector widths are changed and processing units having vector registers of differing widths do not require different code.
摘要翻译：处理单元在程序中执行向量宽度指令，并且处理单元获得并提供将用于处理可变向量处理指令的适当向量寄存器的宽度。然后，当处理单元在程序中执行可变向量处理指令时，处理单元使用具有与适当向量寄存器相同宽度的指令的适当向量寄存器处理可变向量处理指令。处理单元获得的宽度可以小于适当向量寄存器的实际宽度，并且可以由处理单元设置。以这种方式，可以使用一组用于向量处理的指令来支持许多不同的向量宽度。如果矢量宽度改变，并且具有不同宽度的矢量寄存器的处理单元不需要不同的代码，则不需要新的指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式