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1. 发明授权

US07920419B2 Isolated P-well architecture for a memory device 有权
标题翻译：用于存储器件的隔离P-阱结构
公开(公告)号：US07920419B2
公开(公告)日：2011-04-05
申请号：US12362914
申请日：2009-01-30
申请人： Prashant Damle , Krishna Parat , Shafqat Ahmed
发明人： Prashant Damle , Krishna Parat , Shafqat Ahmed
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/3427 , H01L27/11519 , H01L27/11524
摘要： A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read, and verify operations, the isolated P-wells may be coupled to source.
摘要翻译：一种存储器件和通过将非易失性存储器阵列中的P阱分离来防止或减少编程干扰的方法。在编程操作期间，分离的P阱可以耦合到可以被选择或禁止的相应位线，并且可以处于不同的电压。在擦除，读取和验证操作期间，隔离的P阱可以耦合到源。

2. 发明申请

US20150055407A1 SET AND RESET OPERATION IN PHASE CHANGE MEMORY AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS 有权
标题翻译：相变存储器中的设置和复位操作及相关技术和配置
公开(公告)号：US20150055407A1
公开(公告)日：2015-02-26
申请号：US14010417
申请日：2013-08-26
申请人： Davide Mantegazza , Kiran Pangal , Gerard H. Joyce , Prashant Damle , Derchang Kau , Davide Fugazza
发明人： Davide Mantegazza , Kiran Pangal , Gerard H. Joyce , Prashant Damle , Derchang Kau , Davide Fugazza
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0092
摘要： Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了在相变存储器（PCM）设备中的字线路径隔离的技术和配置。在一个实施例中，一种方法包括增加通过相变存储器（PCM）器件的存储器单元的电流，其中存储器单元与电容器耦合，并且随后增加电流，产生通过存储器单元的瞬态电流，由放电电容器来重置存储单元。在另一个实施例中，一种方法包括增加通过相变存储器（PCM）器件的存储器单元的电流，并且控制电流大于阈值电流并且低于存储器单元的保持电流以设置存储器单元。可以描述和/或要求保护其他实施例。

3. 发明申请

US20140089762A1 Techniques Associated with a Read and Write Window Budget for a Two Level Memory System 有权
标题翻译：与两级存储器系统的读写窗口预算相关的技术
公开(公告)号：US20140089762A1
公开(公告)日：2014-03-27
申请号：US13627380
申请日：2012-09-26
申请人： KIRAN PANGAL , PRASHANT DAMLE
发明人： KIRAN PANGAL , PRASHANT DAMLE
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G06F11/1008 , G06F11/1048 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C16/10 , G11C16/26
摘要： Examples are disclosed for techniques associated with a read and write window budget for a two level memory (2LM) system. In some examples, a read and write window budget may be established for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory. Other examples are described and claimed.
摘要翻译：公开了与用于二级存储器（2LM）系统的读取和写入窗口预算相关联的技术的示例。在一些示例中，可以为包括第一级存储器和第二级存储器的2LM系统建立读和写窗口预算。所建立的读写窗口预算可以包括第一组存储器地址和第二级存储器的第二组存储器地址的组合。与第二组存储器地址相关联的非易失性存储器单元的单元阈值电压分布相比，第一组存储器地址可以与具有更宽的单元阈值电压分布的非易失性存储单元相关联。根据一些示例，建立的读和写窗口预算可以是满足给定量的存储器的完成时间阈值和给定量的存储器的可接受的错误率阈值的策略的一部分，当满足对该存储器的读取或写入请求时，二级内存其他的例子被描述和要求保护。

4. 发明申请

US20110090739A1 INDEPENDENT WELL BIAS MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：在存储设备中独立的良好BIAS管理
公开(公告)号：US20110090739A1
公开(公告)日：2011-04-21
申请号：US12582458
申请日：2009-10-20
申请人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
发明人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
摘要翻译：提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

5. 发明授权

US08498159B2 Independent well bias management in a memory device 有权
标题翻译：存储器件中的独立阱偏置管理
公开(公告)号：US08498159B2
公开(公告)日：2013-07-30
申请号：US13465328
申请日：2012-05-07
申请人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
发明人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483
摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
摘要翻译：提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

6. 发明申请

US20120218824A1 INDEPENDENT WELL BIAS MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：在存储设备中独立的良好BIAS管理
公开(公告)号：US20120218824A1
公开(公告)日：2012-08-30
申请号：US13465328
申请日：2012-05-07
申请人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
发明人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
摘要翻译：提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

7. 发明授权

US08174893B2 Independent well bias management in a memory device 有权
标题翻译：存储器件中的独立阱偏置管理
公开(公告)号：US08174893B2
公开(公告)日：2012-05-08
申请号：US12582458
申请日：2009-10-20
申请人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
发明人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483
摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
摘要翻译：提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

8. 发明申请

US20100195383A1 Isolated P-well Architecture for a Memory Device 有权
标题翻译：用于存储器件的隔离P阱结构
公开(公告)号：US20100195383A1
公开(公告)日：2010-08-05
申请号：US12362914
申请日：2009-01-30
申请人： Prashant Damle , Krishna Parat , Shafqat Ahmed
发明人： Prashant Damle , Krishna Parat , Shafqat Ahmed
IPC分类号： G11C16/02 , G11C16/06 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/3427 , H01L27/11519 , H01L27/11524
摘要： A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read, and verify operations, the isolated P-wells may be coupled to source.
摘要翻译：一种存储器件和通过将非易失性存储器阵列中的P阱分离来防止或减少编程干扰的方法。在编程操作期间，分离的P阱可以耦合到可以被选择或禁止的相应位线，并且可以处于不同的电压。在擦除，读取和验证操作期间，隔离的P阱可以耦合到源。

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