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1. 发明申请

US20140089875A1 Method and Apparatus for Optimizing Memory-Built-In-Self Test 有权
公开(公告)号：US20140089875A1
公开(公告)日：2014-03-27
申请号：US13625733
申请日：2012-09-24
申请人： Puneet Arora , Navneet Kaushik , Steven Gregor , Norman Card
发明人： Puneet Arora , Navneet Kaushik , Steven Gregor , Norman Card
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/14
摘要： Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.

2. 发明授权

US08271226B2 Testing state retention logic in low power systems 有权
标题翻译：在低功率系统中测试状态保持逻辑
公开(公告)号：US08271226B2
公开(公告)日：2012-09-18
申请号：US12147428
申请日：2008-06-26
申请人： Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
发明人： Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
IPC分类号： G06F3/00 , G06F3/01 , G06F3/06 , G06F13/10
CPC分类号： G01R31/318575
摘要： A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.
摘要翻译：一种测试集成电路（IC）的方法包括：将一系列数据加载到保持数据值的电路元件链中，其中至少一些电路元件的输出连接到相邻电路元件的输入，因此值顺序地通过用于装载值的链输入和用于卸载值的链输出之间的链，以及第一电路元件，包括用于在与IC相关的功率变化期间保存值的保持元件。该方法还包括：从保留元素中的数据序列中保存值; 以及访问所述保留元件，以从所述数据序列验证所保存的值的准确性。

3. 发明申请

US20220279448A1 THERMAL MANAGEMENT BY SYSTEMATIC NETWORK RECONFIGURATION 有权
公开(公告)号：US20220279448A1
公开(公告)日：2022-09-01
申请号：US17621929
申请日：2019-07-30
申请人： Edwin IUN , Puneet ARORA
发明人： Edwin IUN , Puneet ARORA
IPC分类号： H04W52/02 , H04W52/38
摘要： Methods and systems for thermal management of a telecommunications network having at least one wireless radio equipment system in communication with a plurality of radio heads. The wireless radio equipment system has a thermal management component. Each of the plurality of radio heads has a high operating temperature threshold. The methods and system configured to monitor the operating temperature of the plurality of radio heads by the thermal management component. If a determination by the thermal management component that at least one of the radio heads exceeds its high operating temperature threshold, a reconfiguring of the telecommunications network to reduce the operating temperature of the at least one of the plurality of radio heads.

4. 发明授权

US08719761B2 Method and apparatus for optimizing memory-built-in-self test 有权
标题翻译：用于优化内存自身测试的方法和装置
公开(公告)号：US08719761B2
公开(公告)日：2014-05-06
申请号：US13625682
申请日：2012-09-24
申请人： Norman Card , Puneet Arora , Steven Gregor , Navneet Kaushik
发明人： Norman Card , Puneet Arora , Steven Gregor , Navneet Kaushik
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/14
摘要： Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.
摘要翻译：使用优化的存储器内置自检（MBIST）方法来测试存储器，包括生成用于存储器的紧凑模型。成本函数由影响MBIST的估计参数构成，用户可以为参数分配相对权重。估计参数包括MBIST区域，布线拥塞和定时开销，以及功耗和时序。使用优化技术最小化成本函数，从而对存储器件进行优化分组，并为MBIST测试提供优化的计划。估计的参数可以从由从各种存储器件实验导出的数据构建的紧凑模型中导出。这种方法允许电路设计者在运行完整的设计流程之前生成和修改分组和计划，从而节省时间和成本，同时仍然实现高质量的结果。

5. 发明授权

US08688465B2 Pharmaceutical representative expense report management software, systems, and methodologies 有权
标题翻译：制药代理费用报表管理软件，系统和方法
公开(公告)号：US08688465B2
公开(公告)日：2014-04-01
申请号：US11925491
申请日：2007-10-26
申请人： Puneet Arora , Margaret K. Feltz , Sayee Natarajan , Jake Stahl , Bert Weinstein
发明人： Puneet Arora , Margaret K. Feltz , Sayee Natarajan , Jake Stahl , Bert Weinstein
IPC分类号： G06Q50/00
CPC分类号： G06Q50/22 , G06F19/00 , G06Q10/10 , G06Q40/12
摘要： Electronic assigning of expense data related to sales calls to customers such as health care professionals (HCPs) aids in complying with local, state, federal, or other regulatory reporting requirements and guidelines. The method includes providing expense report data and presenting a line-item entry of the report on a display. Through a user interface, one or more customers included within a database are selected. An expense amount associated with the line-item entry is automatically allocated into dollar amounts among the selected customer(s) and entries in the database are updated for each selected customer to now include the allocated dollar amounts.
摘要翻译：与医疗保健专业人员（HCP）等客户的销售电话相关的费用数据的电子分配有助于遵守当地，州，联邦或其他监管报告要求和指南。该方法包括提供费用报告数据并在显示器上呈现报告的行项目条目。通过用户界面，选择数据库中包含的一个或多个客户端。与订单项项目相关联的费用金额在所选择的客户之间自动分配为美元，并且针对每个所选客户更新数据库中的条目，以现在包括分配的美元金额。

6. 发明申请

US20080103822A1 PHARMACEUTICAL REPRESENTATIVE EXPENSE REPORT MANAGEMENT SOFTWARE, SYSTEMS, AND METHODOLOGIES 有权
标题翻译：药品代理费用报告管理软件，系统和方法
公开(公告)号：US20080103822A1
公开(公告)日：2008-05-01
申请号：US11925491
申请日：2007-10-26
申请人： Puneet Arora , Margaret K. Feltz , Sayee Natarajan , Jake Stahl , Bert Weinstein
发明人： Puneet Arora , Margaret K. Feltz , Sayee Natarajan , Jake Stahl , Bert Weinstein
IPC分类号： G06Q40/00
CPC分类号： G06Q50/22 , G06F19/00 , G06Q10/10 , G06Q40/12
摘要： Electronic assigning of expense data related to sales calls to customers such as health care professionals (HCPs) aids in complying with local, state, federal, or other regulatory reporting requirements and guidelines. The method includes providing expense report data and presenting a line-item entry of the report on a display. Through a user interface, one or more customers included within a database are selected. An expense amount associated with the line-item entry is automatically allocated into dollar amounts among the selected customer(s) and entries in the database are updated for each selected customer to now include the allocated dollar amounts.
摘要翻译：与医疗保健专业人员（HCP）等客户的销售电话相关的费用数据的电子分配有助于遵守当地，州，联邦或其他监管报告要求和指南。该方法包括提供费用报告数据并在显示器上呈现报告的行项目条目。通过用户界面，选择数据库中包含的一个或多个客户端。与订单项项目相关联的费用金额在所选择的客户之间自动分配为美元，并且针对每个所选客户更新数据库中的条目，以现在包括分配的美元金额。

7. 发明申请

US20160099656A1 NON-ISOLATED AC-DC CONVERSION POWER SUPPLY 审中-公开
标题翻译：非隔离型AC-DC转换电源
公开(公告)号：US20160099656A1
公开(公告)日：2016-04-07
申请号：US14509041
申请日：2014-10-07
申请人： Shivam Mishra , Puneet Arora , Mohammad Kamil , Amit Tiwari
发明人： Shivam Mishra , Puneet Arora , Mohammad Kamil , Amit Tiwari
IPC分类号： H02M7/06
CPC分类号： H02M7/06 , H02M1/4208 , H02M3/07 , Y02B70/126
摘要： A non-isolated capacitive AC-DC conversion power supply includes a current limiting input module that receives AC input power and has an output capacitor that supplies DC power. Charge storage stages have charge storage capacitors, a rectifier supplying rectified current from the input module to charge the charge storage capacitors and the output capacitor during a first part-cycle of the AC input power. The charge storage stages also include current amplifiers and unidirectional elements that conduct discharge current from the charge storage capacitors to charge the output capacitor during a second part-cycle of the AC input power. Ground of the DC output can be connected to the live AC input.
摘要翻译：非隔离电容式AC-DC转换电源包括限流输入模块，其接收交流输入功率并具有提供直流电力的输出电容器。充电存储阶段具有电荷存储电容器，整流器在输入模块的第一部分周期期间从输入模块提供整流电流以对电荷存储电容器和输出电容器充电。电荷存储阶段还包括电流放大器和单向元件，其在AC输入功率的第二部分周期期间传导来自电荷存储电容器的放电电流，以对输出电容器充电。直流输出的地线可以连接到实时交流输入。

8. 发明授权

US08990749B2 Method and apparatus for optimizing memory-built-in-self test 有权
标题翻译：用于优化内存自身测试的方法和装置
公开(公告)号：US08990749B2
公开(公告)日：2015-03-24
申请号：US13625733
申请日：2012-09-24
申请人： Puneet Arora , Navneet Kaushik , Steven Gregor , Norman Card
发明人： Puneet Arora , Navneet Kaushik , Steven Gregor , Norman Card
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/14
摘要： Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.
摘要翻译：使用优化的存储器内置自检（MBIST）方法来测试存储器，包括生成用于存储器的紧凑模型。成本函数由影响MBIST的估计参数构成，用户可以为参数分配相对权重。估计参数包括MBIST区域，布线拥塞和定时开销，以及功耗和时序。使用优化技术最小化成本函数，从而对存储器件进行优化分组，并为MBIST测试提供优化的计划。估计的参数可以从由从各种存储器件实验导出的数据构建的紧凑模型中导出。这种方法允许电路设计者在运行完整的设计流程之前生成和修改分组和计划，从而节省时间和成本，同时仍然实现高质量的结果。

9. 发明授权

US08677196B1 Low cost production testing for memory 有权
标题翻译：内存低成本生产测试
公开(公告)号：US08677196B1
公开(公告)日：2014-03-18
申请号：US13164370
申请日：2011-06-20
申请人： Steven Lee Gregor , Norman Robert Card , Hanumantha Raya , Puneet Arora
发明人： Steven Lee Gregor , Norman Robert Card , Hanumantha Raya , Puneet Arora
IPC分类号： G11C29/00
CPC分类号： G11C29/1201
摘要： Embodiments provide methods, systems, devices, and/or machine readable storage medium for memory built-in self testing (memory BIST) that may not require JTAG. Embodiments may provide less chip overhead through the use of one or more direct access pins. Embodiments may provide simple checks to determine if the memories on a chip are good or bad with minimal cost, for example. In some cases, the memory BIST may determine whether or not memories are good when the chip powers on. Some embodiments may also perform stress testing on the memories to force early life failures of the memories. Embodiments do not necessarily have to diagnose failures.
摘要翻译：实施例提供了可能不需要JTAG的用于存储器内置自检（存储器BIST）的方法，系统，设备和/或机器可读存储介质。实施例可以通过使用一个或多个直接访问引脚来提供更少的芯片开销。实施例可以提供简单的检查来确定芯片上的存储器是否良好或低成本，例如最小的成本。在某些情况下，当芯片通电时，存储器BIST可以确定存储器是否良好。一些实施例还可以对存储器执行压力测试以迫使存储器的早期生命故障。实施例不一定必须诊断故障。

10. 发明申请

US20090326854A1 TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS 有权
标题翻译：低功耗系统中的测试状态保持逻辑
公开(公告)号：US20090326854A1
公开(公告)日：2009-12-31
申请号：US12147428
申请日：2008-06-26
申请人： Krishna CHAKRAVADHANULA , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
发明人： Krishna CHAKRAVADHANULA , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
IPC分类号： G01R31/317
CPC分类号： G01R31/318575
摘要： A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.
摘要翻译：一种测试集成电路（IC）的方法包括：将一系列数据加载到保持数据值的电路元件链中，其中至少一些电路元件的输出连接到相邻电路元件的输入，因此值顺序地通过用于装载值的链输入和用于卸载值的链输出之间的链，以及第一电路元件，包括用于在与IC相关的功率变化期间保存值的保持元件。该方法还包括：从保留元素中的数据序列中保存值; 以及访问所述保留元件，以从所述数据序列验证所保存的值的准确性。

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