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1. 发明申请

US20130046941A1 WRITE CIRCUIT, READ CIRCUIT, MEMORY BUFFER AND MEMORY MODULE 有权
标题翻译：写入电路，读取电路，存储器缓冲器和存储器模块
公开(公告)号：US20130046941A1
公开(公告)日：2013-02-21
申请号：US13579201
申请日：2011-08-08
申请人： Qingjiang Ma , Haiyang Li
发明人： Qingjiang Ma , Haiyang Li
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G06F11/1004 , G11C7/1084 , G11C7/1096
摘要： The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer. Advantages of the present invention lie in that: data can be transmitted with a memory controller in a low power consumption manner, and the data transmitted based on conversion control data can be read out of or written into a DDR4 memory chip.
摘要翻译：本发明提供了写入电路，读取电路，存储器缓冲器和存储器模块。写入电路包括：数据采集单元，第一校验单元，数据恢复单元，第一校验数据生成单元，第一调整单元和写单元; 读取电路包括：数据读取单元，第二检查单元，输出数据生成单元，第二检查数据生成单元，第二调整单元和输出单元; 存储器缓冲器包括写入电路和读取电路; 存储器模块包括存储器缓冲器和连接到存储器缓冲器的多个存储器芯片。本发明的优点在于：可以以低功耗方式与存储器控制器一起发送数据，并且可以将基于转换控制数据发送的数据读出或写入DDR4存储器芯片。

2. 发明申请

US20130036287A1 METHOD FOR ALLOCATING ADDRESSES TO DATA BUFFERS IN DISTRIBUTED BUFFER CHIPSET 有权
标题翻译：在分布式缓冲区中分配数据缓冲区的方法
公开(公告)号：US20130036287A1
公开(公告)日：2013-02-07
申请号：US13512507
申请日：2011-10-18
申请人： Huaixiang Chu , Qingjiang Ma
发明人： Huaixiang Chu , Qingjiang Ma
IPC分类号： G06F12/02
CPC分类号： G06F13/16 , G06F13/1673 , G11C7/10 , G11C8/06 , G11C11/4093
摘要： The present invention relates to a method for allocating addresses to data buffers in a distributed buffer chipset, in which a memory controller informs a central buffer of the beginning of address allocation through a Command/Address channel (CA), and then the central buffer informs through a data control channel all the data buffers of preparing for receiving address parameters through respective data channels, and in this way, each data buffer receives and latches the respective address parameter from the memory controller through the respective data, thus avoiding the defect in the prior art that the size of the data buffer and the size of the entire distributed buffer chipset is bigger as several address pins need to be additionally configured in each data buffer to allocate the respective address parameter.
摘要翻译：本发明涉及一种分配缓冲器芯片组中的数据缓冲器的地址分配方法，其中存储器控制器通过命令/地址信道（CA）通知中央缓冲区开始地址分配，然后中央缓冲区通知通过数据控制通道，所有数据缓冲器准备通过相应数据通道接收地址参数，并且以这种方式，每个数据缓冲器通过相应的数据从存储器控制器接收并锁存相应的地址参数，从而避免了现有技术中，数据缓冲器的大小和整个分布式缓冲器芯片组的尺寸较大，因为需要在每个数据缓冲器中额外配置若干地址引脚以分配相应的地址参数。

3. 发明授权

US09026726B2 Data read/write system 有权
标题翻译：数据读/写系统
公开(公告)号：US09026726B2
公开(公告)日：2015-05-05
申请号：US13813355
申请日：2011-08-09
申请人： Haiyang Li , Qingjiang Ma
发明人： Haiyang Li , Qingjiang Ma
IPC分类号： G06F12/00 , G06F12/02 , G06F11/10
CPC分类号： G06F12/00 , G06F11/1004 , G06F12/0246
摘要： The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data output circuit, and a data receiving circuit. The memory module includes a memory buffer and at least two memory chips. The memory buffer includes a second control circuit, a write circuit, and a read circuit. The advantage of the present invention is that, when data is read or written into the memory chip, especially a DDR4 X4 memory chip, low power consumption of interface data transmission can be achieved through a data bus inversion control line DBI.
摘要翻译：本发明提供一种数据读/写系统。数据读/写系统包括存储器控制器和存储器模块。存储器控制器包括第一控制电路，数据输出电路和数据接收电路。存储器模块包括存储器缓冲器和至少两个存储器芯片。存储缓冲器包括第二控制电路，写电路和读电路。本发明的优点在于，当数据被读取或写入存储器芯片，特别是DDR4X4存储器芯片时，可以通过数据总线反转控制线DBI实现接口数据传输的低功耗。

4. 发明申请

US20070159221A1 System and method for clock signal synchronization 失效
标题翻译：时钟信号同步的系统和方法
公开(公告)号：US20070159221A1
公开(公告)日：2007-07-12
申请号：US10596987
申请日：2004-12-13
申请人： Qingjiang Ma , James Gao , Yongqing Ren
发明人： Qingjiang Ma , James Gao , Yongqing Ren
IPC分类号： H03L7/00
CPC分类号： H04L7/042
摘要： A system (101) for clock signal synchronization includes a data analyzer (104) and a synchronized clock signal generator (105) coupled to an RC oscillator (103). The data analyzer (104) generates a digital control signal representing the number of cycles of a reference signal of the RC oscillator (103) during an eight-bit period of an incoming token packet. The synchronized signal clock generator (105) uses the digital control signal to lock a clock signal to packets that have the same bit rate as the token packet.
摘要翻译：用于时钟信号同步的系统（101）包括耦合到RC振荡器（103）的数据分析器（104）和同步时钟信号发生器（105）。数据分析器（104）在输入令牌分组的八位周期期间产生表示RC振荡器（103）的参考信号的周期数的数字控制信号。同步信号时钟发生器（105）使用数字控制信号将时钟信号锁定到与令牌分组具有相同比特率的分组。

5. 发明授权

US09201817B2 Method for allocating addresses to data buffers in distributed buffer chipset 有权
标题翻译：分配缓冲区芯片组数据缓冲区地址分配方法
公开(公告)号：US09201817B2
公开(公告)日：2015-12-01
申请号：US13512507
申请日：2011-10-18
申请人： Huaixiang Chu , Qingjiang Ma
发明人： Huaixiang Chu , Qingjiang Ma
IPC分类号： G06F3/00 , G06F13/16 , G11C8/06 , G11C7/10 , G11C11/4093
CPC分类号： G06F13/16 , G06F13/1673 , G11C7/10 , G11C8/06 , G11C11/4093
摘要： The present invention relates to a method for allocating addresses to data buffers in a distributed buffer chipset, in which a memory controller informs a central buffer of the beginning of address allocation through a Command/Address channel (CA), and then the central buffer informs through a data control channel all the data buffers of preparing for receiving address parameters through respective data channels, and in this way, each data buffer receives and latches the respective address parameter from the memory controller through the respective data, thus avoiding the defect in the prior art that the size of the data buffer and the size of the entire distributed buffer chipset is bigger as several address pins need to be additionally configured in each data buffer to allocate the respective address parameter.
摘要翻译：本发明涉及一种分配缓冲器芯片组中的数据缓冲器的地址分配方法，其中存储器控制器通过命令/地址信道（CA）通知中央缓冲区开始地址分配，然后中央缓冲区通知通过数据控制通道，所有数据缓冲器准备通过相应数据通道接收地址参数，并且以这种方式，每个数据缓冲器通过相应的数据从存储器控制器接收并锁存相应的地址参数，从而避免了现有技术中，数据缓冲器的大小和整个分布式缓冲器芯片组的尺寸较大，因为需要在每个数据缓冲器中额外配置若干地址引脚以分配相应的地址参数。

6. 发明申请

US20130124816A1 DEVICE REQUIRING ADDRESS ALLOCATION, DEVICE SYSTEM AND ADDRESS ALLOCATION METHOD 有权
标题翻译：需要地址分配的设备，设备系统和地址分配方法
公开(公告)号：US20130124816A1
公开(公告)日：2013-05-16
申请号：US13586317
申请日：2012-08-15
申请人： Chunyi LI , Qingjiang MA
发明人： Chunyi LI , Qingjiang MA
IPC分类号： G06F12/02
CPC分类号： G06F12/0669 , G06F13/16
摘要： A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals. When determining availability of currently allocated address information, the device requiring address allocation stores currently allocated address information, and modifies address allocation flag information to address information already allocated, thereby achieving address allocation for the devices.
摘要翻译：需要地址分配的设备，设备系统和地址分配方法。设备系统中的控制装置通过总线将当前分配的地址信息和竞争启动信号发送到需要在设备系统中进行地址分配的每个设备，并且需要地址分配的设备具有地址分配标志信息，即没有分配地址信息地址争用信号。当输出地址争用信号时，需要地址分配的每个设备根据是否需要地址分配的地址分配的其他设备是否没有分配地址信息来确定当前分配的地址信息是否可用已经输出地址争用信号。当确定当前分配的地址信息的可用性时，需要地址分配的设备存储当前分配的地址信息，并且修改地址分配标志信息以寻址已经分配的信息，从而实现设备的地址分配。

7. 发明授权

US07864906B2 System and method for clock signal synchronization 失效
标题翻译：时钟信号同步的系统和方法
公开(公告)号：US07864906B2
公开(公告)日：2011-01-04
申请号：US10596987
申请日：2004-12-13
申请人： Qingjiang Ma , James Y. Gao , Yongqing Ren
发明人： Qingjiang Ma , James Y. Gao , Yongqing Ren
IPC分类号： H04L7/00
CPC分类号： H04L7/042
摘要： A system (101) for clock signal synchronization includes a data analyzer (104) and a synchronized clock signal generator (105) coupled to an RC oscillator (103). The data analyzer (104) generates a digital control signal representing the number of cycles of a reference signal of the RC oscillator (103) during an eight-bit period of an incoming token packet. The synchronized signal clock generator (105) uses the digital control signal to lock a clock signal to packets that have the same bit rate as the token packet.
摘要翻译：用于时钟信号同步的系统（101）包括耦合到RC振荡器（103）的数据分析器（104）和同步时钟信号发生器（105）。数据分析器（104）在输入令牌分组的八位周期期间产生表示RC振荡器（103）的参考信号的周期数的数字控制信号。同步信号时钟发生器（105）使用数字控制信号将时钟信号锁定到与令牌分组具有相同比特率的分组。

8. 发明授权

US09003154B2 Device requiring address allocation, device system and address allocation method 有权
标题翻译：设备需要地址分配，设备系统和地址分配方法
公开(公告)号：US09003154B2
公开(公告)日：2015-04-07
申请号：US13586317
申请日：2012-08-15
申请人： Chunyi Li , Qingjiang Ma
发明人： Chunyi Li , Qingjiang Ma
IPC分类号： G06F12/02 , G06F13/16 , G06F12/06
CPC分类号： G06F12/0669 , G06F13/16
摘要： A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals. When determining availability of currently allocated address information, the device requiring address allocation stores currently allocated address information, and modifies address allocation flag information to address information already allocated, thereby achieving address allocation for the devices.
摘要翻译：需要地址分配的设备，设备系统和地址分配方法。设备系统中的控制装置通过总线将当前分配的地址信息和竞争启动信号发送到需要在设备系统中进行地址分配的每个设备，并且需要地址分配的设备具有地址分配标志信息，即没有分配地址信息地址争用信号。当输出地址争用信号时，需要地址分配的每个设备根据是否需要地址分配的地址分配的其他设备是否没有分配地址信息来确定当前分配的地址信息是否可用已经输出地址争用信号。当确定当前分配的地址信息的可用性时，需要地址分配的设备存储当前分配的地址信息，并且修改地址分配标志信息以寻址已经分配的信息，由此实现设备的地址分配。

9. 发明授权

US08843801B2 Write circuit, read circuit, memory buffer and memory module 有权
标题翻译：写电路，读电路，存储器缓冲器和存储器模块
公开(公告)号：US08843801B2
公开(公告)日：2014-09-23
申请号：US13579201
申请日：2011-08-08
申请人： Qingjiang Ma , Haiyang Li
发明人： Qingjiang Ma , Haiyang Li
IPC分类号： H03M13/00 , G11C7/10 , G06F11/10
CPC分类号： G11C7/1006 , G06F11/1004 , G11C7/1084 , G11C7/1096
摘要： The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer.
摘要翻译：本发明提供了写入电路，读取电路，存储器缓冲器和存储器模块。写入电路包括：数据采集单元，第一校验单元，数据恢复单元，第一校验数据生成单元，第一调整单元和写单元; 读取电路包括：数据读取单元，第二检查单元，输出数据生成单元，第二检查数据生成单元，第二调整单元和输出单元; 存储器缓冲器包括写入电路和读取电路; 存储器模块包括存储器缓冲器和连接到存储器缓冲器的多个存储器芯片。

10. 发明申请

US20130132660A1 DATA READ/WRITE SYSTEM 有权
标题翻译：数据读/写系统
公开(公告)号：US20130132660A1
公开(公告)日：2013-05-23
申请号：US13813355
申请日：2011-08-09
申请人： Haiyang Li , Qingjiang Ma
发明人： Haiyang Li , Qingjiang Ma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/00 , G06F11/1004 , G06F12/0246
摘要： The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data output circuit, and a data receiving circuit. The memory module includes a memory buffer and at least two memory chips. The memory buffer includes a second control circuit, a write circuit, and a read circuit. The advantage of the present invention is that, when data is read or written into the memory chip, especially a DDR4 X4 memory chip, low power consumption of interface data transmission can be achieved through a data bus inversion control line DBI.
摘要翻译：本发明提供一种数据读/写系统。数据读/写系统包括存储器控制器和存储器模块。存储器控制器包括第一控制电路，数据输出电路和数据接收电路。存储器模块包括存储器缓冲器和至少两个存储器芯片。存储缓冲器包括第二控制电路，写电路和读电路。本发明的优点在于，当数据被读取或写入存储器芯片，特别是DDR4X4存储器芯片时，可以通过数据总线反转控制线DBI实现接口数据传输的低功耗。

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