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1. 发明授权

US07496731B2 Two dimensional addressing of a matrix-vector register array 有权
标题翻译：矩阵向量寄存器阵列的二维寻址
公开(公告)号：US07496731B2
公开(公告)日：2009-02-24
申请号：US11850920
申请日：2007-09-06
申请人： Peter A. Sandon , R. Michael P. West
发明人： Peter A. Sandon , R. Michael P. West
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3012 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30109 , G06F9/30145 , G06F15/8084
摘要： A method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2, K≧2, and B≧1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.
摘要翻译：一种处理矩阵数据的方法。该处理器包括M个独立的向量寄存器文件，其适于集中地存储L个数据元素的矩阵。每个数据元素都有B位二进制位。矩阵具有N行和M列，L = N * M。每列有K个子列。 N> = 2，M> = 2，K> = 2，B> = 1。每行和每个子列都是可寻址的。处理器不会重复存储L个数据元素。矩阵包括一组阵列，使得每个数组是矩阵的行或子列。处理器可以执行对该组阵列的第一阵列执行操作的指令，使得以相对于第一阵列的数据元素的选择性执行该操作。

2. 发明授权

US5874967A Graphics system and process for blending graphics display layers 失效
标题翻译：用于混合图形显示层的图形系统和过程
公开(公告)号：US5874967A
公开(公告)日：1999-02-23
申请号：US931926
申请日：1997-09-17
申请人： R. Michael P. West , Edward K. Evans , Stephen J. Stratz
发明人： R. Michael P. West , Edward K. Evans , Stephen J. Stratz
IPC分类号： G09G5/06 , G06T1/20 , G06T11/00 , G06T15/50 , G09G5/14 , G06T3/00
CPC分类号： G06T1/20 , G06T11/00 , G06T15/503
摘要： A graphics system comprising a format processor for receiving display data including pixel data and color-blending information for at least two (2) separate display layers, a color blender and color processors. The pixel data includes color information for the display layers. The color-blending information determines weighting factors for use in blending the colors of the display layers. The format processor outputs separate streams of pixel data, one for each display layer, as well as the weighting factors. Each stream of pixel data outputted by the processor is inputted into a corresponding color processor that assigns colors to a particular display layer according to the color information in the corresponding pixel data. The color blender blends the colors assigned to the display layers according to the weighting factors.
摘要翻译：一种图形系统，包括用于接收包括用于至少两（2）个分立显示层的像素数据和颜色混合信息的显示数据的格式处理器，彩色混合器和彩色处理器。像素数据包括显示层的颜色信息。颜色混合信息确定用于混合显示层的颜色的加权因子。格式处理器输出单独的像素数据流，每个显示层一个以及加权因子。由处理器输出的每个像素数据流被输入到根据相应像素数据中的颜色信息将颜色分配给特定显示层的相应颜色处理器。混色机根据加权因子混合分配给显示层的颜色。

3. 发明授权

US5471570A Hardware XOR sprite for computer display systems 失效
标题翻译：用于计算机显示系统的硬件XOR精灵
公开(公告)号：US5471570A
公开(公告)日：1995-11-28
申请号：US176128
申请日：1993-12-30
申请人： Darwin P. Rackley , R. Michael P. West
发明人： Darwin P. Rackley , R. Michael P. West
IPC分类号： G09G5/02 , G09G5/06 , G09G5/08 , G09G5/38 , G06T11/00
CPC分类号： G09G5/08 , G09G5/06
摘要： Method and apparatus for adjusting the color of the sprite in display systems, so that the sprite is always distinctively visible irrespective of the underlying displayed data. A palette DAC of a display system is provided with sprite control logic, which derives the color of a sprite to be overlaid on an image displayed on a video display unit of a display system by inverting only the most significant bit (MSB) of each of the red, green and blue pixel data components of the underlying image. In a preferred embodiment, the sprite control logic circuit comprises first, second and third multiplexors (MUXes) each having a first input connected to receive the MSB of the red, green and blue pixel data components of the underlying image, respectively, and a second input connected to receive the output of first, second and third XOR gates, respectively. Each of the first, second and third XOR gates similarly have a first input connected to receive the MSB of the red, green and blue pixel data components of the underlying image, respectively, and a second input connected to receive sprite data from a sprite RAM, which sprite data represents a sprite character to be overlaid on the displayed image.
摘要翻译：用于调整显示系统中的精灵颜色的方法和装置，使得子画面总是可视地显示，而不管底层显示的数据如何。显示系统的调色板DAC具有子画面控制逻辑，该精灵控制逻辑通过仅反转显示系统的视频显示单元的最高有效位（MSB）来导出要重叠在显示系统的视频显示单元上的图像上的子画面的颜色底层图像的红色，绿色和蓝色像素数据组件。在优选实施例中，子画面控制逻辑电路包括第一，第二和第三多路复用器（MUX），每个多路复用器（MUX）分别具有连接以分别接收底层图像的红色，绿色和蓝色像素数据分量的MSB的第一输入，输入端分别接收第一，第二和第三异或门的输出。第一，第二和第三异或门中的每一个类似地具有连接以分别接收底层图像的红色，绿色和蓝色像素数据分量的MSB的第一输入和连接以从子画面RAM接收精灵数据的第二输入，哪个子画面数据表示要覆盖在显示图像上的子画面字符。

4. 发明授权

US07949853B2 Two dimensional addressing of a matrix-vector register array 有权
标题翻译：矩阵向量寄存器阵列的二维寻址
公开(公告)号：US07949853B2
公开(公告)日：2011-05-24
申请号：US11950474
申请日：2007-12-05
申请人： Peter A. Sandon , R. Michael P. West
发明人： Peter A. Sandon , R. Michael P. West
IPC分类号： G06F15/173 , G06F15/76
CPC分类号： G06F9/3012 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30109 , G06F9/30145 , G06F15/8084
摘要： A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2, K≧2, and B≧1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.
摘要翻译：用于处理矩阵数据的处理器。处理器包括M个独立的向量寄存器文件，其适于集中地存储L个数据元素的矩阵。每个数据元素都有B位二进制位。矩阵具有N行和M列，L = N * M。每列有K个子列。 N≥2，M≥2，K≥2，B≥1。每行和每个子列都是可寻址的。处理器不会重复存储L个数据元素。矩阵包括一组阵列，使得每个数组是矩阵的行或子列。处理器可以执行对该组阵列的第一阵列执行操作的指令，使得以相对于第一阵列的数据元素的选择性执行该操作。

5. 发明授权

US07386703B2 Two dimensional addressing of a matrix-vector register array 有权
标题翻译：矩阵向量寄存器阵列的二维寻址
公开(公告)号：US07386703B2
公开(公告)日：2008-06-10
申请号：US10715688
申请日：2003-11-18
申请人： Peter A. Sandon , R. Michael P. West
发明人： Peter A. Sandon , R. Michael P. West
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3012 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30109 , G06F9/30145 , G06F15/8084
摘要： A processor and method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2, K≧1, and B≧1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.
摘要翻译：一种用于处理矩阵数据的处理器和方法。处理器包括M个独立的向量寄存器文件，其适于集中地存储L个数据元素的矩阵。每个数据元素都有B位二进制位。矩阵具有N行和M列，L = N * M。每列有K个子列。 N> = 2，M> = 2，K> = 1，B> = 1。每行和每个子列都是可寻址的。处理器不会重复存储L个数据元素。矩阵包括一组阵列，使得每个数组是矩阵的行或子列。处理器可以执行对该组阵列的第一阵列执行操作的指令，使得以相对于第一阵列的数据元素的选择性执行该操作。

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