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    • 2. 发明授权
    • Compiling memory dereferencing instructions from software to hardware in an electronic design
    • 从电子设计的软件到硬件编译内存取消引用指令
    • US07203912B2
    • 2007-04-10
    • US10896431
    • 2004-07-21
    • Rajat MoonaRussell Alan Klein
    • Rajat MoonaRussell Alan Klein
    • G06F17/50
    • G06F17/505
    • Electronic system functionality can be initially implemented as software code (e.g., in programming languages such as C, C++ or Pascal) and selectively converted to a hardware representation such as in hardware description language (e.g., VHDL, Verilog, HandelC, BachC, SpecC and System Verilog). In one aspect, software code representations comprising memory dereferencing operations (e.g., related to pointers, arrays and structs) may also be converted to a hardware representation. The newly converted hardware representation may be given control of a main communications network (e.g., system bus) of the electronic system to control the execution of the memory dereferencing operations (e.g., related to pointers, arrays and structs). In one embodiment, bus control may be via a bus control interface adapted for a particular kind of communications network (e.g., a processor bus, a system bus, a hierarchical bus, a cross bar, a multiplexer bus, a switch network and a point to point network). In another embodiment, a software memory dereferencer for executing memory dereferencing operations may be provided.
    • 电子系统功能可以最初实现为软件代码(例如,在诸如C,C ++或Pascal的编程语言中),并且选择性地转换为硬件表示,例如硬件描述语言(例如,VHDL,Verilog,HandelC,BachC,SpecC和 系统Verilog)。 在一个方面,包括存储器取消引用操作(例如,与指针,数组和结构相关)的软件代码表示也可以被转换为硬件表示。 新转换的硬件表示可以被给予电子系统的主要通信网络(例如,系统总线)的控制,以控制存储器解引用操作的执行(例如,与指针,数组和结构相关)。 在一个实施例中,总线控制可以经由适于特定类型的通信网络的总线控制接口(例如,处理器总线,系统总线,分层总线,交叉条,复用器总线,交换机网络和点 到点网络)。 在另一实施例中,可以提供用于执行存储器解引用操作的软件存储器解引用器。
    • 6. 发明授权
    • Repartitioning performance estimation in a hardware-software system
    • 在硬件 - 软件系统中重新分配性能估计
    • US06856951B2
    • 2005-02-15
    • US10295193
    • 2002-11-15
    • Rajat MoonaRussell Alan Klein
    • Rajat MoonaRussell Alan Klein
    • G06F9/45G06F9/455G06F17/50
    • G06F11/3447G06F11/3457G06F2201/87
    • A tool is described herein for optimizing the design of a hardware-software system. The tool allows a designer to evaluate the potential improvement in system performance that may be realized by moving selected software components of the system to a hardware implementation. In one aspect, the tool automatically generates a performance profile of an original form of the system. The performance profile of the original form of the system may be used to select software components of the system to be moved to hardware. In another aspect, the tool generates an estimated performance profile of a repartitioned form of the system by modifying the performance profile of the system. The estimated performance profile of the repartitioned system is compared to the performance profile of the original form of the system to verify benefits, if any, of repartitioning. Such verification is accomplished without the need to actually repartitioning the system or measuring the performance of the entire repartitioned system.
    • 这里描述了一种用于优化硬件 - 软件系统的设计的工具。 该工具允许设计人员通过将系统的选定软件组件移动到硬件实现来评估系统性能的潜在改进。 在一个方面,该工具自动生成系统的原始形式的性能配置文件。 系统原始形式的性能特征可用于选择要移动到硬件的系统的软件组件。 在另一方面,该工具通过修改系统的性能特征来生成重新分配的系统的性能轮廓。 将重新分配的系统的估计性能曲线与系统原始形式的性能曲线进行比较,以验证重新分配的利益(如果有的话)。 这种验证是在不需要实际重新分配系统或测量整个重新分配的系统的性能的情况下完成的。
    • 7. 发明申请
    • Compiling memory dereferencing instructions from software to hardware in an electronic design
    • 从电子设计的软件到硬件编译内存取消引用指令
    • US20060031791A1
    • 2006-02-09
    • US10896431
    • 2004-07-21
    • Rajat MoonaRussell Klein
    • Rajat MoonaRussell Klein
    • G06F17/50
    • G06F17/505
    • Electronic system functionality can be initially implemented as software code (e.g., in programming languages such as C, C++ or Pascal) and selectively converted to a hardware representation such as in hardware description language (e.g., VHDL, Verilog, HandelC, BachC, SpecC and System Verilog). In one aspect, software code representations comprising memory dereferencing operations (e.g., related to pointers, arrays and structs) may also be converted to a hardware representation. The newly converted hardware representation may be given control of a main communications network (e.g., system bus) of the electronic system to control the execution of the memory dereferencing operations (e.g., related to pointers, arrays and structs). In one embodiment, bus control may be via a bus control interface adapted for a particular kind of communications network (e.g., a processor bus, a system bus, a hierarchical bus, a cross bar, a multiplexer bus, a switch network and a point to point network). In another embodiment, a software memory dereferencer for executing memory dereferencing operations may be provided.
    • 电子系统功能可以最初实现为软件代码(例如,在诸如C,C ++或Pascal的编程语言中),并且选择性地转换为诸如硬件描述语言(例如,VHDL,Verilog,HandelC,BachC,SpecC和 系统Verilog)。 在一个方面,包括存储器取消引用操作(例如,与指针,数组和结构相关)的软件代码表示也可以被转换为硬件表示。 新转换的硬件表示可以被给予电子系统的主要通信网络(例如,系统总线)的控制,以控制存储器解引用操作的执行(例如,与指针,数组和结构相关)。 在一个实施例中,总线控制可以经由适于特定类型的通信网络的总线控制接口(例如,处理器总线,系统总线,分层总线,交叉条,复用器总线,交换机网络和点 到点网络)。 在另一实施例中,可以提供用于执行存储器解引用操作的软件存储器解引用器。
    • 8. 发明申请
    • Area optimization of hardware for algorithms by optimizing sizes of variables of the algorithm
    • 通过优化算法变量的大小来优化算法的硬件
    • US20060020574A1
    • 2006-01-26
    • US10896630
    • 2004-07-21
    • Rajat MoonaRussell KleinRamachandran Gopalakrishnan
    • Rajat MoonaRussell KleinRamachandran Gopalakrishnan
    • G06F17/30
    • G06F11/3447G06F17/505G06F2201/865
    • Described herein are methods and systems for optimizing area related to hardware implementation of algorithms. The algorithms may be related to functionality of an embedded system, for instance. System functionality may be initially implemented in software and converted to hardware implementation. Prior to implementing system functionality in actual hardware, algorithms for selected system functionality or desirable all system functionality may be evaluated to determine values attained by selected variables or desirably all the variables comprised therein. In one embodiment, a probe may applied to the original software code to determine a maximum value and a minimum value corresponding to each of the variables of the algorithm (or at least one such variable) may be tracked across one or more invocations of functions (or other code components) of the algorithm comprising such variables. Based on such tracked values, a minimum size (e.g., in bit-width), for each of the variables, needed to express the various values attained by the variables may be determined. The original software code implementing system functionality may then be modified to declare or otherwise specify an optimal (e.g., the minimum bit-width needed to express values attained) bit-width, which can result in reduced area for a hardware implementation.
    • 这里描述了用于优化与算法的硬件实现相关的区域的方法和系统。 例如,算法可能与嵌入式系统的功能有关。 系统功能可以最初在软件中实现并转换成硬件实现。 在实际硬件中实现系统功能之前,可以对所选择的系统功能或期望的所有系统功能性的算法进行评估,以确定所选变量所获得的值,或期望所包含的所有变量。 在一个实施例中,可以将探测器应用于原始软件代码以确定对应于算法(或至少一个此类变量)中的每个变量的最大值,并且可以跨越一个或多个函数调用来跟踪最大值 或其他代码组件)。 基于这样的跟踪值,可以确定用于表示由变量获得的各种值所需的每个变量的最小大小(例如,位宽度)。 然后,可以修改原始软件代码实现系统功能以声明或以其他方式指定最佳(例如,表示获得的值所需的最小位宽)位宽度,这可能导致硬件实现的面积减小。