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    • 3. 发明授权
    • Digital to analog convertor
    • 数模转换器
    • US06850177B2
    • 2005-02-01
    • US10477684
    • 2002-05-13
    • Brian DonovanRay S. McKaig
    • Brian DonovanRay S. McKaig
    • H03M1/82H03M1/68
    • H03M1/68H03M1/822
    • A method and circuit are provided for converting a digital signal to an analog signal in the form of a pulse width modulated (PWM) pulse (20). The PWM pulse is generated during an output cycle of a pulse generator to form a pulsetrain output of pulses at a fixed frequency whose widths are determined by dynamically changing digital input data. The method includes the steps of dividing the digital data signal into most significant bit (MSB) and least significant bit (LSB) portions. A PWM pulse is initiated at the beginning of an output cycle and continues while the MSB portion counts down in a counter (24). At the same time, the LSB portion of the digital data signal is converted to a precise phase delay signal which is a subcycle of an oscillator controlling the counter. This phase delay signal is generated after the termination of the MSB count, and halts the high period of the PWM pulse during the output cycle. When the output cycle ends, the process is repeated with the next digital signal.
    • 提供一种方法和电路,用于将数字信号转换成脉冲宽度调制(PWM)脉冲(20)形式的模拟信号。 在脉冲发生器的输出周期期间产生PWM脉冲以形成固定频率的脉冲的脉冲串输出,其宽度通过动态地改变数字输入数据来确定。 该方法包括将数字数据信号分成最高有效位(MSB)和最低有效位(LSB)部分的步骤。 PWM脉冲在输出周期开始时启动,并在MSB部分在计数器(24)中向下计数时继续。 同时,数字数据信号的LSB部分被转换为精确的相位延迟信号,该相位延迟信号是控制计数器的振荡器的子周期。 该相位延迟信号在MSB计数结束后产生,并在输出周期中停止PWM脉冲的高电平周期。 当输出周期结束时,使用下一个数字信号重复该过程。
    • 4. 发明授权
    • High speed precision analog to digital convertor
    • 高速精密模数转换器
    • US06445326B1
    • 2002-09-03
    • US09602596
    • 2000-06-22
    • Brian T. DonovanRay S. McKaigWilliam B. Dress
    • Brian T. DonovanRay S. McKaigWilliam B. Dress
    • H03M112
    • H03M1/14H03M1/502H03M1/504
    • An analog to digital convertor includes a pulse width modulated circuit (PWM) responsive to an analog parameter of an analog signal. The PWM circuit generates a pulse having a duty cycle proportional to the analog parameter. A counter generates a plurality of counterpulses during the pulse duty cycle and a sub-cycle pulse generator generates a series of subcycle pulses during each of the counterpulses. A latch circuit latches the state of the subcycle pulse generator at a predetermined time relative to the termination of the PWM pulse and a logic circuit counts the number of counterpulses which are generated during the PWM pulse. A most significant bit number is represented by the number of counter-pulses and a least significant bit number is determined by the state of the subcycle pulses in the latch. These two numbers added together provide a digital number representative of the analog parameter.
    • 模数转换器包括响应于模拟信号的模拟参数的脉宽调制电路(PWM)。 PWM电路产生具有与模拟参数成比例的占空比的脉冲。 计数器在脉冲占空比期间产生多个反向脉冲,并且子周期脉冲发生器在每个对称脉冲期间产生一系列子周期脉冲。 锁存电路相对于PWM脉冲的终止在预定时间锁存子周期脉冲发生器的状态,并且逻辑电路对在PWM脉冲期间产生的反向脉冲数进行计数。 最高有效位数由反脉冲数表示,最低有效位数由锁存器中的子循环脉冲的状态决定。 这两个数字相加在一起提供了代表模拟参数的数字数字。