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1. 发明申请

US20090106468A1 Hierarchical Bus Structure and Memory Access Protocol for Multiprocessor Systems 有权
标题翻译：多处理器系统的分层总线结构和存储器访问协议
公开(公告)号：US20090106468A1
公开(公告)日：2009-04-23
申请号：US12341778
申请日：2008-12-22
申请人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
发明人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
IPC分类号： G06F13/368
CPC分类号： G06F13/1657
摘要： A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.
摘要翻译：公开了一种分层总线结构，其中处理器簇在层次结构内布置和互连，以便于通过共享存储器进行处理器通信。总线结构非常适用于其中嵌入式处理器集群并行处理语音流的语音处理应用，尽管架构不受限制。还公开了一种存储器访问协议，其中共享存储器访问操作的地址和数据部分被执行为在时间上分离的单独的总线事务，使得来自不同处理器的多个并发存储器访问操作可以在共享总线上交错。

2. 发明授权

US07469308B2 Hierarchical bus structure and memory access protocol for multiprocessor systems 有权
标题翻译：多处理器系统的分层总线结构和存储器访问协议
公开(公告)号：US07469308B2
公开(公告)日：2008-12-23
申请号：US11496746
申请日：2006-07-31
申请人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
发明人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
IPC分类号： G06F13/00 , G06F13/368 , G06F15/167 , C06C5/06
CPC分类号： G06F13/1657
摘要： A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.
摘要翻译：公开了一种分层总线结构，其中处理器簇在层次结构内布置和互连，以便于通过共享存储器进行处理器通信。总线结构非常适用于其中嵌入式处理器集群并行处理语音流的语音处理应用，尽管架构不受限制。还公开了一种存储器访问协议，其中共享存储器访问操作的地址和数据部分被执行为在时间上分离的单独的总线事务，使得来自不同处理器的多个并发存储器访问操作可以在共享总线上交错。

3. 发明授权

US5754468A Compact multiport static random access memory cell 失效
标题翻译：紧凑型多端口静态随机存取存储单元
公开(公告)号：US5754468A
公开(公告)日：1998-05-19
申请号：US673732
申请日：1996-06-26
申请人： Richard F. Hobson
发明人： Richard F. Hobson
IPC分类号： H01L27/11 , G11C11/00
CPC分类号： H01L27/1104 , Y10S257/903
摘要： A new static random access memory cell for standard logic CMOS processes with three or more metal layers is detailed. The method uses three P-type and three N-type MOS transistors to form a two-port memory cell, which can be configured to perform as a one port, or a two port memory cell. In addition to standard memory applications, specialty memories, like a First-In First-Out (FIFO) buffer, which can benefit from the natural 2-port structure of our invention, are particularly appealing. Additional ports can be added for applications like a 3-port microprocessor register array.
摘要翻译：详细介绍了具有三个或更多个金属层的标准逻辑CMOS工艺的新的静态随机存取存储单元。该方法使用三个P型和三个N型MOS晶体管来形成双端口存储单元，其可被配置为执行一个端口或两端口存储单元。除了标准存储器应用之外，可以从本发明的自然2端口结构中受益的专业存储器（例如先进先出（FIFO）缓冲器）特别吸引人。可以为3端口微处理器寄存器阵列等应用添加其他端口。

4. 发明授权

US08190803B2 Hierarchical bus structure and memory access protocol for multiprocessor systems 有权
标题翻译：多处理器系统的分层总线结构和存储器访问协议
公开(公告)号：US08190803B2
公开(公告)日：2012-05-29
申请号：US12341778
申请日：2008-12-22
申请人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
发明人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
IPC分类号： G06F13/368 , G06F3/00 , G06F13/362 , G06F13/372 , G06F15/167 , G06F13/00
CPC分类号： G06F13/1657
摘要： A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.
摘要翻译：公开了一种分层总线结构，其中处理器簇在层次结构内布置和互连，以便于通过共享存储器进行处理器通信。总线结构非常适用于其中嵌入式处理器集群并行处理语音流的语音处理应用，尽管架构不受限制。还公开了一种存储器访问协议，其中共享存储器访问操作的地址和数据部分被执行为在时间上分离的单独的总线事务，使得来自不同处理器的多个并发存储器访问操作可以在共享总线上交错。

5. 发明申请

US20110047354A1 Processor Cluster Architecture and Associated Parallel Processing Methods 有权
标题翻译：处理器集群架构和相关并行处理方法
公开(公告)号：US20110047354A1
公开(公告)日：2011-02-24
申请号：US12940799
申请日：2010-11-05
申请人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
发明人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
IPC分类号： G06F9/38 , G06F15/76 , G06F9/312
CPC分类号： G06F9/5033 , G06F9/445 , G06F9/5061 , G06F9/5066 , G06F2209/5012 , G06F2209/5017
摘要： A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.
摘要翻译：一种并行处理架构，其包括共享公共代码分配总线的嵌入式处理器集群。代码页或代码块通过代码分配总线同时加载到这些处理器（通常是分配给特定任务的所有处理器）的一些或全部的相应程序存储器中，并且由这些处理器并行执行。任务控制处理器确定分配给特定任务的所有处理器何时完成执行当前代码页，然后将新代码页（例如，任务内的下一个顺序代码页）加载到这些处理器的程序存储器中执行。集群内的处理器优选地共享用于从更高级处理器接收数据输入并向其提供数据输出的公共存储器（每个群集1）。多个互连的集群可以集成在公共集成电路装置内。

6. 发明授权

US07840778B2 Processor cluster architecture and associated parallel processing methods 有权
标题翻译：处理器集群架构及相关并行处理方法
公开(公告)号：US07840778B2
公开(公告)日：2010-11-23
申请号：US11468826
申请日：2006-08-31
申请人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
发明人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
IPC分类号： G06F9/00
CPC分类号： G06F9/5033 , G06F9/445 , G06F9/5061 , G06F9/5066 , G06F2209/5012 , G06F2209/5017
摘要： A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.
摘要翻译：一种并行处理架构，其包括共享公共代码分配总线的嵌入式处理器集群。代码页或代码块通过代码分配总线同时加载到这些处理器（通常是分配给特定任务的所有处理器）的一些或全部的相应程序存储器中，并且由这些处理器并行执行。任务控制处理器确定分配给特定任务的所有处理器何时完成执行当前代码页，然后将新代码页（例如，任务内的下一个顺序代码页）加载到这些处理器的程序存储器中执行。集群内的处理器优选地共享用于从更高级处理器接收数据输入并向其提供数据输出的公共存储器（每个群集1）。多个互连的集群可以集成在公共集成电路装置内。

7. 发明授权

US06959372B1 Processor cluster architecture and associated parallel processing methods 有权
标题翻译：处理器集群架构及相关并行处理方法
公开(公告)号：US06959372B1
公开(公告)日：2005-10-25
申请号：US10369182
申请日：2003-02-18
申请人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
发明人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
IPC分类号： G06F12/00
CPC分类号： G06F9/5033 , G06F9/445 , G06F9/5061 , G06F9/5066 , G06F2209/5012 , G06F2209/5017
摘要： A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.
摘要翻译：一种并行处理架构，其包括共享公共代码分配总线的嵌入式处理器集群。代码页或代码块通过代码分配总线同时加载到这些处理器（通常是分配给特定任务的所有处理器）的一些或全部的相应程序存储器中，并且由这些处理器并行执行。任务控制处理器确定分配给特定任务的所有处理器何时完成执行当前代码页，然后将新代码页（例如，任务内的下一个顺序代码页）加载到这些处理器的程序存储器中执行。集群内的处理器优选地共享用于从更高级处理器接收数据输入并向其提供数据输出的公共存储器（每个群集1）。多个互连的集群可以集成在公共集成电路装置内。

8. 发明授权

US07210139B2 Processor cluster architecture and associated parallel processing methods 有权
标题翻译：处理器集群架构及相关并行处理方法
公开(公告)号：US07210139B2
公开(公告)日：2007-04-24
申请号：US11255597
申请日：2005-10-20
申请人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
发明人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
IPC分类号： G06F9/45
CPC分类号： G06F9/5033 , G06F9/445 , G06F9/5061 , G06F9/5066 , G06F2209/5012 , G06F2209/5017
摘要： A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.
摘要翻译：一种并行处理架构，其包括共享公共代码分配总线的嵌入式处理器集群。代码页或代码块通过代码分配总线同时加载到这些处理器（通常是分配给特定任务的所有处理器）的一些或全部的相应程序存储器中，并且由这些处理器并行执行。任务控制处理器确定分配给特定任务的所有处理器何时完成执行当前代码页，然后将新代码页（例如，任务内的下一个顺序代码页）加载到这些处理器的程序存储器中执行。集群内的处理器优选地共享用于从更高级处理器接收数据输入并向其提供数据输出的公共存储器（每个群集1）。多个互连的集群可以集成在公共集成电路装置内。

9. 发明授权

US07085866B1 Hierarchical bus structure and memory access protocol for multiprocessor systems 有权
标题翻译：多处理器系统的分层总线结构和存储器访问协议
公开(公告)号：US07085866B1
公开(公告)日：2006-08-01
申请号：US10369340
申请日：2003-02-18
申请人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
发明人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
IPC分类号： G06F13/362 , G06F12/00
CPC分类号： G06F13/1657
摘要： A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.
摘要翻译：公开了一种分层总线结构，其中处理器簇在层次结构内布置和互连，以便于通过共享存储器进行处理器通信。总线结构非常适用于其中嵌入式处理器集群并行处理语音流的语音处理应用，尽管架构不受限制。还公开了一种存储器访问协议，其中共享存储器访问操作的地址和数据部分被执行为在时间上分离的单独的总线事务，使得来自不同处理器的多个并发存储器访问操作可以在共享总线上交错。

10. 发明授权

US08489857B2 Processor cluster architecture and associated parallel processing methods 有权
标题翻译：处理器集群架构及相关并行处理方法
公开(公告)号：US08489857B2
公开(公告)日：2013-07-16
申请号：US12940799
申请日：2010-11-05
申请人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
发明人： Richard F. Hobson , Bill Ressl , Allan R. Dyck
IPC分类号： G06F9/00
CPC分类号： G06F9/5033 , G06F9/445 , G06F9/5061 , G06F9/5066 , G06F2209/5012 , G06F2209/5017
摘要： A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.
摘要翻译：一种并行处理架构，其包括共享公共代码分配总线的嵌入式处理器集群。代码页或代码块通过代码分配总线同时加载到这些处理器（通常是分配给特定任务的所有处理器）的一些或全部的相应程序存储器中，并且由这些处理器并行执行。任务控制处理器确定分配给特定任务的所有处理器何时完成执行当前代码页，然后将新代码页（例如，任务内的下一个顺序代码页）加载到这些处理器的程序存储器中执行。集群内的处理器优选地共享用于从更高级处理器接收数据输入并向其提供数据输出的公共存储器（每个群集1）。多个互连的集群可以集成在公共集成电路装置内。

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