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1. 发明授权

US08504884B2 Threshold voltage techniques for detecting an imminent read failure in a memory array 有权
标题翻译：用于检测存储器阵列中即将发生的读取故障的阈值电压技术
公开(公告)号：US08504884B2
公开(公告)日：2013-08-06
申请号：US12608405
申请日：2009-10-29
申请人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
发明人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
IPC分类号： G11C29/00
CPC分类号： G11C29/50004 , G11C16/26 , G11C29/42 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.
摘要翻译：用于检测存储器阵列中即将发生的读取故障的技术包括确定在正常读取验证电压电平下的初始阵列完整性检查期间不显示不能校正的纠错码（ECC）的存储器阵列是否显示出不可校正的ECC 在随后的阵列完整性检查期间读取读取验证电压电平。当在后续阵列完整性检查期间存储器阵列呈现不可校正的ECC读取时，该技术还包括提供针对存储器阵列的迫在眉睫的读取失败的指示。在这种情况下，余量读取验证电压电平与正常读取验证电压电平不同。

2. 发明授权

US08427877B2 Digital method to obtain the I-V curves of NVM bitcells 有权
标题翻译：数字方法来获得NVM位单元的I-V曲线
公开(公告)号：US08427877B2
公开(公告)日：2013-04-23
申请号：US13025712
申请日：2011-02-11
申请人： Chen He , Richard K. Eguchi
发明人： Chen He , Richard K. Eguchi
IPC分类号： G11C16/06
CPC分类号： G11C29/50 , G11C16/04 , G11C29/50004
摘要： A calibration table (160) of reference current (Iref) values and associated digital register settings is used during user test/diagnostics mode by varying the Iref values by changing the digital register settings and searching the transitioning gate voltage (Vg) of each bitcell at each Iref value to obtain the bitcell I-V curve using a digitally tunable gate voltage control (117) and reference current circuit (123) under control of a test module or circuit (110).
摘要翻译：在用户测试/诊断模式期间，通过改变数字寄存器设置并搜索每个位单元的转换栅极电压（Vg）来改变Iref值，使用参考电流（Iref）值和相关联的数字寄存器设置的校准表（160）每个Iref值以在测试模块或电路（110）的控制下使用数字可调门电压控制（117）和参考电流电路（123）来获得位单元IV曲线。

3. 发明申请

US20120327710A1 ADAPTIVE WRITE PROCEDURES FOR NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的自适应写入程序
公开(公告)号：US20120327710A1
公开(公告)日：2012-12-27
申请号：US13170009
申请日：2011-06-27
申请人： CHEN HE , Richard K. Eguchi
发明人： CHEN HE , Richard K. Eguchi
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/30
摘要： A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A level of the voltage is compared to a reference. If the level of the voltage is below the reference, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells, wherein the reduced number of memory cells is a first subset of the memory cells.
摘要翻译：一种方法包括使用电荷泵的电压对存储器阵列的存储器单元执行写入操作到第一逻辑状态。使用电荷泵的电压对存储器阵列的存储单元执行写入操作的一部分。将电压的电平与参考值进行比较。如果电压的电平低于参考值，则通过在减少数量的存储器单元上提供电压来减小电荷泵上的负载，继续以电压水平升高的写入操作，其中减少数量的存储器单元是存储器单元的第一子集。

4. 发明申请

US20120072794A1 NON-VOLATILE MEMORY (NVM) WITH IMMINENT ERROR PREDICTION 有权
标题翻译：非易失性存储器（NVM）具有明显的错误预测
公开(公告)号：US20120072794A1
公开(公告)日：2012-03-22
申请号：US12886861
申请日：2010-09-21
申请人： RICHARD K. EGUCHI , DANIEL HADAD , CHEN HE , KATRINA M. PROSPERI , JON W. WEILEMANN, II
发明人： RICHARD K. EGUCHI , DANIEL HADAD , CHEN HE , KATRINA M. PROSPERI , JON W. WEILEMANN, II
IPC分类号： G11C29/50 , G06F11/07
CPC分类号： G11C29/38 , G06F11/073 , G06F11/0754 , G11C16/3418
摘要： A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.
摘要翻译：提供了一种用于确定非易失性存储器阵列即将发生故障的方法和系统。该方法包括：执行存储器阵列的第一阵列完整性读取，直到检测到错误; 确定所述误差不是可纠正的纠错码（ECC），其中与所述误差相关联的第一字线电压被表征为第一阈值电压; 执行存储器阵列的第二阵列完整性读取，直到存储器阵列的所有位指示预定状态，其中与指示预定状态的所有位相关联的第二字线电压是第二阈值电压; 以及将所述第一阈值电压和所述第二阈值电压之间的差值比较为预定值。

5. 发明授权

US07640389B2 Non-volatile memory having a multiple block erase mode and method therefor 有权
标题翻译：具有多块擦除模式的非易失性存储器及其方法
公开(公告)号：US07640389B2
公开(公告)日：2009-12-29
申请号：US11364129
申请日：2006-02-28
申请人： Richard K. Eguchi , Jon S. Choy
发明人： Richard K. Eguchi , Jon S. Choy
IPC分类号： G06F12/00 , G06F13/28 , G06F13/00
CPC分类号： G06F12/0246
摘要： A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.
摘要翻译：非易失性存储器可以具有并行擦除多个块，用于相对较少数量的擦除操作。这样可以节省用户设置存储器的时间，因为擦除操作相对较慢。并行擦除的问题涉及具有不同程序/擦除历史的不同块，结果是具有不同历史的块被擦除不同。因此，在执行预定数量的擦除周期之后，防止并行擦除的能力。这通过允许并行擦除操作直到预定数量的擦除操作被计数来实现。在达到预定数量之后，产生并行擦除模式禁止信号，以防止进一步的并行擦除周期。计数和预定数量被保持在用户无法访问的非易失性存储器的小块中。

6. 发明授权

US07545679B1 Electrical erasable programmable memory transconductance testing 有权
标题翻译：电可擦除可编程存储器跨导测试
公开(公告)号：US07545679B1
公开(公告)日：2009-06-09
申请号：US11966068
申请日：2007-12-28
申请人： Richard K. Eguchi , Chen He , Ronald J. Syzdek
发明人： Richard K. Eguchi , Chen He , Ronald J. Syzdek
IPC分类号： G11C16/00
CPC分类号： G11C29/50 , G11C16/04 , G11C2029/5002 , G11C2029/5006
摘要： A test method determines if an array of a Flash EEPROM circuit has a bit cell with a transconductance (gm) that is deficient. The method preconditions all bit cells of the array to a particular programmed state and then determines whether any of the bit cells exhibit undesirable operating characteristics by reading each bit cell to determine whether its transconductance is less than desirable.
摘要翻译：测试方法确定闪存EEPROM电路的阵列是否具有缺陷的跨导（gm）的位单元。该方法将阵列的所有比特单元预先调整到特定的编程状态，然后通过读取每个比特单元来确定其中的任何一个比特单元是否表现出不期望的运行特性，以确定其跨导是否小于期望值。

7. 发明申请

US20080120526A1 MEMORY DEVICE WITH ADJUSTABLE READ REFERENCE BASED ON ECC AND METHOD THEREOF 有权
标题翻译：基于ECC的可调整读取引用的存储器件及其方法
公开(公告)号：US20080120526A1
公开(公告)日：2008-05-22
申请号：US11560533
申请日：2006-11-16
申请人： Richard K. Eguchi , Ronald J. Syzdek
发明人： Richard K. Eguchi , Ronald J. Syzdek
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/1008 , G11C16/28
摘要： A first value from a set of bit cells of a sector of a non-volatile memory device is sensed based on a first read reference. A second value from the set of bit cells is sensed based on a second read reference different than the first read reference. A third read reference for a first subsequent access to the sector of the non-volatile memory device is determined based on at least one of the first read reference and the second read reference in response to determining a first error code condition associated with the first value and a second error code condition associated with the second value represent different error code conditions.
摘要翻译：基于第一读取参考来感测来自非易失性存储器件的扇区的一组位单元的第一值。基于与第一读取参考不同的第二读取参考来感测来自位单元组的第二值。响应于确定与第一值相关联的第一错误代码条件，基于第一读取参考和第二读取参考中的至少一个来确定用于对非易失性存储器设备的扇区的第一后续访问的第三读取参考并且与第二值相关联的第二错误代码条件表示不同的错误代码条件。

8. 发明授权

US06937047B2 Integrated circuit with test pad structure and method of testing 有权
标题翻译：具有测试板结构的集成电路和测试方法
公开(公告)号：US06937047B2
公开(公告)日：2005-08-30
申请号：US10634484
申请日：2003-08-05
申请人： Tu-Anh Tran , Richard K. Eguchi , Peter R. Harper , Chu-Chung Lee , William M. Williams , Lois Yong
发明人： Tu-Anh Tran , Richard K. Eguchi , Peter R. Harper , Chu-Chung Lee , William M. Williams , Lois Yong
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3187 , G11C29/48 , G01R31/02
CPC分类号： G11C29/1201 , G01R31/2884 , G01R31/31715 , G01R31/3187 , G11C29/48 , H01L2224/05554
摘要： A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.
摘要翻译：半导体器件在外围具有大量用于引线键合的接合焊盘。该半导体器件具有模块以及其他电路，但该模块比其他电路需要更长的测试时间。由于至少部分地由具有内置自检（BIST）电路的半导体器件，模块测试需要相对较少数量的接合焊盘（模块接合焊盘）。这些模块接合焊盘的功能在半导体器件的顶表面和内部复制，模块测试焊盘明显大于外围的焊盘。具有大的测试垫可以延长探针，从而提高并行测试能力。通过测试接口接口实现复制功能，使得模块接合焊盘和模块测试焊盘不必一起短路。

9. 发明授权

US09329921B2 Imminent read failure detection using high/low read voltage levels 有权
标题翻译：使用高/低读取电压电平的即时读取故障检测
公开(公告)号：US09329921B2
公开(公告)日：2016-05-03
申请号：US14262074
申请日：2014-04-25
申请人： Jon W. Weilemann, II , Richard K. Eguchi
发明人： Jon W. Weilemann, II , Richard K. Eguchi
IPC分类号： G11C29/00 , G06F11/07 , G06F11/10
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/1048 , G11C16/3418 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004 , G11C29/52 , G11C2029/0409
摘要： Methods and systems are disclosed for imminent read failure detection using high/low read voltage levels. In certain embodiments, data stored within an array of non-volatile memory (NVM) cells is checked using read voltage levels below and above a normal read voltage level. An imminent read failure is then indicated if errors are detected within the same address for both voltage checks. Further, data stored can be checked using read voltage levels that are incrementally decreased below and incrementally increased above a normal read voltage level. An imminent read failure is then indicated if read errors are detected within the same address for both voltage sweeps and if high/low read voltage levels triggering faults differ by less than a predetermined threshold value. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.
摘要翻译：公开了使用高/低读取电压电平即将发生的读取故障检测的方法和系统。在某些实施例中，使用低于和高于正常读取电压电平的读取电压电平来检查存储在非易失性存储器（NVM）单元阵列内的数据。然后，如果两个电压检查在同一地址内检测到错误，则会显示即将发生的读取失败。此外，可以使用逐渐减小到低于正常读取电压电平并递增地增加的读取电压电平来检查存储的数据。然后，如果在两个电压扫描的相同地址内检测到读取错误，并且触发故障的高/低读取电压电平差异小于预定阈值，则会立即指示即将发生的读取失败。可以使用地址排序器，纠错码（ECC）逻辑和偏置发生器来实现即将发生的故障检测。

10. 发明授权

US09318163B2 Robust memory start-up using clock counter 有权
标题翻译：使用时钟计数器强大的内存启动
公开(公告)号：US09318163B2
公开(公告)日：2016-04-19
申请号：US13789017
申请日：2013-03-07
申请人： Richard K. Eguchi , Craig D. Gunderson
发明人： Richard K. Eguchi , Craig D. Gunderson
IPC分类号： G11C7/20 , G11C5/14 , G11C7/22
CPC分类号： G11C5/148 , G11C7/20 , G11C7/22
摘要： In accordance with at least one embodiment, a clock counter on a system (for example, a system-on-a-chip (SOC) or other system) is utilized to count a number of a clock edges of a memory clock within a predefined time based on a predetermined system clock frequency and, therefore, to determine whether the memory clock for a memory array (for example, a non-volatile memory (NVM) array or other memory array) is correct or not. The system is directed to wait until the count is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the system such that the application can react to it.
摘要翻译：根据至少一个实施例，系统（例如，片上系统（SOC）或其他系统）上的时钟计数器被用于对预定义的内存中的存储器时钟的时钟边缘的数量进行计数基于预定的系统时钟频率，因此确定存储器阵列（例如，非易失性存储器（NVM）阵列或其他存储器阵列）的存储器时钟是否正确。系统被引导等待直到计数在预期的范围内，然后再转到启动过程中的下一个步骤。如果超过允许的最大启动时间，系统会发送错误信号，以便应用程序可以对其进行响应。

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